• System Level Product Development Engineer

    NVIDIA (Santa Clara, CA)
    … + Partner with other engineering groups including ASIC, DFT, ATE, silicon validation , fab process, software and quality teams to coordinate efforts and ... creative solutions for system level diag, verification and post-silicon validation of some of the industry's most complex semiconductor...and as a member of highly productive team + Software skills for statistical large data analysis + Experience… more
    NVIDIA (06/17/25)
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  • Low Power Design/Methodology Engineer

    Qualcomm (San Diego, CA)
    …solution into wireless SoC chips and front-end design flows. + Work closely with system/ software /test team to enable the low power feature in wireless SoC product. + ... Work closely with system/ software /test team to enable functional safety feature in automotive...related field and 4+ years of ASIC design, verification, validation , integration, or related work experience. OR Master's degree… more
    Qualcomm (05/15/25)
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  • Staff R&D Project Engineer - JJMT…

    J&J Family of Companies (Irvine, CA)
    …Johnson & Johnson MedTech, Electrophysiology, is recruiting an **Staff R&D Project Engineer ** located in Irvine, California. This role is on-site with flexibility ... journey to wellness. Learn more at https://www.jnj.com/medtech The Staff R&D Project Engineer provides engineering and design services to Advanced R&D. The Senior… more
    J&J Family of Companies (07/15/25)
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  • ASIC Engineer , Design Verification

    Meta (Menlo Park, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... (SoC) for data center applications. As a Design Verification Engineer , you will be part of an agile team...ample opportunities to partner and collaborate with full stack software , hardware, ASIC Design, Emulation and Post-Silicon teams towards… more
    Meta (07/11/25)
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  • ASIC Engineer , Design Verification

    Meta (Menlo Park, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a team working with the best in the industry,… more
    Meta (07/11/25)
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  • ASIC Engineer , Design Verification

    Meta (Menlo Park, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of a agile team...ample opportunities to partner and collaborate with full stack software , hardware, ASIC Design, Emulation and Post-Silicon teams towards… more
    Meta (07/11/25)
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  • Senior Fluids Engineer

    Element Materials Technology (San Bernardino, CA)
    …expanding team. As a member of the operations team, the Senior Fluids Engineer performs a variety of routine and non-routine testing assignments within the ... timely and accurate test results under minimal direct supervision. The Senior Fluids Engineer positions must be proficient in a number of core business and technical… more
    Element Materials Technology (07/10/25)
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  • Bioinformatics Engineer

    Stanford University (Stanford, CA)
    Bioinformatics Engineer **School of Medicine, Stanford, California, United States** Information Analytics Post Date Jul 02, 2025 Requisition # 106782 Stanford ... University is seeking a Bioinformatics Engineer to manage and analyze large amounts of information,...to provide a platform for functional genomics research and validation to improve diagnosis in Mendelian disease through integrated… more
    Stanford University (07/03/25)
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  • Senior Communications Systems Engineer

    AECOM (Los Angeles, CA)
    …us. **Job Description** **AECOM** is currently seeking a **Senior Communications Systems Engineer ** with specialized skills in Rail and Transit Systems, to join our ... procedures and reports in support of design verification and validation during the project life cycle. + Produce Issued...experience in rail and transit systems. + California Professional Engineer License is preferred, but not required. + Master's… more
    AECOM (06/26/25)
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  • ASIC Design Engineer - Design & Timing…

    Cisco (San Jose, CA)
    ASIC Design Engineer - Design & Timing Constraints Apply (https://jobs.cisco.com/jobs/Login?projectId=1439367) + Location:San Jose, California, US + Area of ... in every facet of chip design, from architecture to validation , using the latest silicon technologies to create groundbreaking...into a single system. With tightly integrated hardware and software solutions, you'll gain exposure to all aspects of… more
    Cisco (06/25/25)
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