• Sr . Substrate CAD Layout Eng, Annapurna…

    Amazon (Cupertino, CA)
    …deliver results that help our customers change the world. We are seeking an experienced Senior Substrate CAD layout Engineer for the next generation of our ML ... and want to reach beyond what is possible today. As a Substrate/PCB layout engineer , you will participate in the definition and implementation of substrate and PCB… more
    Amazon (08/22/25)
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  • Senior FPGA / Rtl Design

    Silvus Technologies (Los Angeles, CA)
    …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA / RTL Design Engineer - Signal Processing_** who will report to the _Director of FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
    Silvus Technologies (10/08/25)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of...skill. + Experience with communication systems on FPGA or ASIC designs. **COMPENSATION** _The pay range is NOT a… more
    Silvus Technologies (08/18/25)
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  • Senior Signal Integrity Engineer

    Palo Alto Networks (Santa Clara, CA)
    …to validate critical interfaces. Within the Hardware team, you collaborate closely with Board Design , ASIC Design , PCB Layout, and Validation Test. You will ... Component Engineers. **Your Impact** + Collaborate with a cross-functional team including: ASIC , Board design , PCB layout, Operations supply base management,… more
    Palo Alto Networks (10/07/25)
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  • Senior Applications Engineer - DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …leaders and innovators who want to make an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob ... Scripts* Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA … more
    Cadence Design Systems, Inc. (10/04/25)
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  • Senior Analog/mixed-signal IC Design

    Cisco (San Jose, CA)
    Senior Analog/mixed-signal IC Design Engineer - Acacia Apply (https://jobs.cisco.com/jobs/Login?projectId=1443040) + Location:San Jose, California, US + ... accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC ....optimize design that will integrate into the ASIC . Our team interacts with other Acacia groups including… more
    Cisco (08/23/25)
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  • Senior Mask Design Engineer

    NVIDIA (Santa Clara, CA)
    Engineer ? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and ... sub-micron CMOS technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI… more
    NVIDIA (08/28/25)
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  • Senior E/E & Semiconductor Engineer

    Capgemini (San Jose, CA)
    …data structures, and algorithms. The ideal candidate will have experience in ASIC design and development within Linux-based environments. Proficiency in version ... and optimize data structures and algorithms to solve complex problems. + Support ASIC design and verification processes. + Develop and manage projects in… more
    Capgemini (09/20/25)
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  • Senior Principal Design Verification…

    BAE Systems (San Diego, CA)
    …awards. Other incentives may be available based on position level and/or job specifics. ** Senior Principal Design Verification Engineer - FPGA - (Sign-on ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who...testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA/ ASIC design and verification tools (Mentor Questa… more
    BAE Systems (09/09/25)
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  • Senior Design for Debug Architect…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and ... logic analyzers and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design , verification, logic synthesis, timing… more
    NVIDIA (09/10/25)
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