• Sr . Silicon Validation Engineer, DVT…

    Amazon (San Diego, CA)
    …around the world. We are seeking a highly motivated and experienced Post-Silicon Verification Engineer with strong expertise in Digital ASIC and modem (PHY ... functionality (PHY/MAC), power, performance, and reliability. * Collaborate closely with design , RTL verification , firmware, and systems teams to root-cause… more
    Amazon (09/07/25)
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  • Electrical Engineer (Associate, Mid-Level,…

    The Boeing Company (El Segundo, CA)
    …* Power Supply * Electronics Packaging * ASIC FPGA Development and Verification * Electrical Design System Engineer * RF Microwave Engineer * Electrical ... has exciting opportunities for **Electrical Engineers (Associate, Mid-Level, or Senior )** to join us as part of our teams...Power Systems & Battery/Solar Array Electrical Design * Antenna RF & Arrays * RF Digital… more
    The Boeing Company (09/07/25)
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  • Digital Verification Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level Digital Design Verification engineer. In this highly ... visible role you will be working on ASIC for data center connectivity applications. Qualifications include: +...Computer Engineering with 6+ years of experience in digital design verification + Hands on experience in… more
    Broadcom (07/11/25)
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  • Senior FPGA Design Engineer

    Silvus Technologies (Irvine, CA)
    …a fulfilling career._ THE OPPORTUNITY Silvus is seeking a full-time **_Senior FPGA Design Engineer_** reporting to the _Director of FPGA Engineering_ on the _FPGA ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
    Silvus Technologies (08/18/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    … Engineer? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic ... sub-micron CMOS technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI… more
    NVIDIA (08/28/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
    NVIDIA (07/16/25)
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  • Senior Silicon Engineer

    Microsoft Corporation (Santa Clara, CA)
    …we are looking for passionate, high-energy engineers to help achieve that mission. As a Senior Silicon Engineer - ASIC verification in the Data Processing ... stage in your career. We are looking for a ** Senior Silicon Engineer** to Join our team! **Responsibilities** +...testing strategies + Work with cross functional teams, architecture, design , verification , partner teams for project execution… more
    Microsoft Corporation (10/01/25)
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  • Senior System SW Engineer, System…

    Palo Alto Networks (Santa Clara, CA)
    …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and ... for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to… more
    Palo Alto Networks (09/19/25)
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  • Senior Emulation Engineer

    Capgemini (Sunnyvale, CA)
    …bugs and ensure design integrity. * Debug: Actively contribute to functional design verification and debug failures to root cause. * Collaborate: Work ... **Position: Emulation Validation/ Verification Engineer** **Location: onsite bay area preferred; any...Experienced Emulation Engineer responsible for validating and debugging complex ASIC and IP designs using the Synopsys ZeBu emulation… more
    Capgemini (08/23/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    …with the testability features coordinated in the RTL. + Work closely with the design / design - verification and PD teams to enable the integration and ... Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose,...be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with… more
    Cisco (09/24/25)
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