• ASIC / FPGA Design Engineer (SMES)

    L3Harris (Camden, NJ)
    …in the amount of $ 15,000 . Job Description: Reporting to the Manager, Engineering ( ASIC / FPGA ), the Senior Member of Engineering Staff (SMES) will be part ... domains in the interest of national security. Job Title: ASIC / FPGA Design Engineer (SMES) Job Code: 26283...Proficient with CDC, RDC. Formal EDA. + Proficient in VHDL . + Proficient with Synthesis/PAR: SDC, Synopsys Synplify, Vivado… more
    L3Harris (07/23/25)
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  • Senior Principal Design Verification…

    BAE Systems (Totowa, NJ)
    …developing, and using constrained random, self-checking testbenches in SystemVerilog/UVM, OVM, and/or VHDL + Experience with FPGA / ASIC design and ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who...Digital Signal Processing + Matlab/Simulink + Working knowledge of VHDL + FPGA Design Experience + Experience… more
    BAE Systems (09/09/25)
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  • Infrastructure Senior Engineer, Low Latency…

    Citigroup (Jersey City, NJ)
    …**Interconnects** (InfiniBand, Slingshot, PCIe, NVLink, UALink, UPI, RoCE) + **HW** (Server, FPGA , GPU, Memory, Cache, over clocking, cooling, ASIC , Quantum, ... the Position** We are looking for an industry wide Senior Subject Matter Expert (SME) - Infrastructure who can...Perl, Shell], CI/CD) + Programming (C, C++, Java, Rust, VHDL , Verilog) + Time Sync (PTP, NTP, GPS, White… more
    Citigroup (09/10/25)
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