• Senior ASIC Clock Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA Networking Clock design team is looking for experienced top notch ASIC design engineer to work on next generation of NVIDIA Networking chips. We're ... role requires working with multiple teams as Architecture, IP, Physical design , Timing and Post-Si teams. Complexity...design next generation clock topologies and modules. + ASIC Clock scheme definition. + Improve Power, Performance, and… more
    NVIDIA (07/24/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer, you will own RTL synthesis and...synthesis and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion… more
    NVIDIA (07/01/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... in SystemVerilog or similar HDL + Solid understanding of physical design and VLSI + Good communication...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
    NVIDIA (07/24/25)
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  • Senior CAD Engineer

    NVIDIA (Santa Clara, CA)
    …the company. What you'll be doing: + Collaborate across internal library, design -enablement, ASIC and physical design teams to develop and support VLSI ... graphics. You'll take on hard problems, partner with world-class design teams, and help deliver the foundational IP that...one of the areas below: + Understanding of VLSI design and place and route flows, CMOS processes, and… more
    NVIDIA (06/05/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... or Computer Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis… more
    NVIDIA (06/10/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd: + Familiarity… more
    NVIDIA (06/24/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    …member of this team, you will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to ... We are now looking for a Senior Power Architecture and Optimization Engineer! NVIDIA prides...power design . + Familiarity with Verilog and ASIC design principles, including knowledge of Power… more
    NVIDIA (06/17/25)
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  • Sr . Design Verification Engineer…

    SpaceX (Sunnyvale, CA)
    Sr . Design Verification Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... make this possible, with the ultimate goal of enabling human life on Mars. SR . DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
    SpaceX (05/23/25)
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  • Sr . Modem / DSP Communication Systems…

    SpaceX (Irvine, CA)
    …engineers who can work with world-class cross-disciplinary teams (firmware, architecture, design , validation, product engineering, ASIC implementation). In this ... Sr . Modem / DSP Communication Systems Engineer (Silicon...broadband communication system + Work in close collaboration with ASIC /FPGA, RF/antenna, and software engineers to design more
    SpaceX (08/08/25)
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  • Sr . Silicon Validation Engineer, SERDES…

    SpaceX (Irvine, CA)
    …environmental conditions specific to space applications + Work closely with the ASIC design team to add/improve testability and define various loopback ... will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation). In this… more
    SpaceX (08/08/25)
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