- NVIDIA (Santa Clara, CA)
- …the choice to join us today. The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and ... CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the...to GPU, CPU and SOC verification team, timing and DFT teams. + Get involved in end-to-end cycle of… more
- NVIDIA (Santa Clara, CA)
- …of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design -for-test ( DFT ) and logic design is a plus. + Proficiency in ... you'll be doing: + Participate in cutting edge Processor design in deep submicron technologies. + Work as part...Work as part of a global circuits team to design the state of the art in silicon monitors… more
- NVIDIA (Santa Clara, CA)
- … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you ... between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing convergence, and… more
- Amazon (San Diego, CA)
- …benches constructed using UVM, System C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with the implementation team . Learn ... field, or equivalent experience . 7+ years in digital design , preferably in communication systems . Experience with products...gone to volume production . Experience in low power design techniques Preferred Qualifications . Master's or Ph.D degree… more
- NVIDIA (Santa Clara, CA)
- …to join our dynamic team today! We are actively looking for Physical design Engineers with RTL2GDS experience to implement complex high performance and low power ... experience. + 6+ years of hands-on experience in Physical design . + Place and route tool experience with Synopsys...Static timing analysis with Synopsys Primetime. + Understanding of DFT and multi-mode timing analysis. + Ability to automate… more
- Palo Alto Networks (Santa Clara, CA)
- …for the manufacturing capabilities to build our next-generation network firewalls. As a senior test engineer , you will be responsible for building advanced test ... for test coverage and serviceability with ICT and boundary scan + Drive DfT ( Design for Testability) and test coverage analyses from early Prototype design … more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior DFX Software Engineer - Machine Learning. Do you like to think creatively and enjoy solving challenges that require innovation? ... you! What you'll be doing: + Develop high performance software to enable design and development of efficient test pattern generation, application of these patterns… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... you! What you'll be doing: + Support the deployment of advanced Design -For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions + Work with multiple… more
- Amazon (San Jose, CA)
- …performant, low-cost satellite bus and payload. As a Sr . PCBA Manufacturing Engineer , you will work across design engineering, supply-chain, quality, and our ... data to drive manufacturability, reliability, and quality objectives in design and development teams. Key job responsibilities - Work...alloys. - Experience with flying probe test systems and DFT - Knowledge of quality tools such as Lean… more
- NVIDIA (Santa Clara, CA)
- …Signal design , characterization, and qualification of BIST and SCAN DFT methodologies. + Knowledgeable in advanced Silicon Process technology such as FinFET ... position within a top-tier organization? In the role of Silicon Product Development Engineer at NVIDIA, you will be instrumental in launching our brand new Data… more