• Sr . ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT , UPF), Power Analysis and STA -Take the lead and work with verification ... teams to define functional coverage -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable… more
    Amazon (07/19/25)
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  • Sr . SoC Design - EM/IR, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …Neural Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design - EM/IR Engineer to continue to innovate on behalf of our ... right vectors for different types of analysis including functional, DFT and other scenarios for which power numbers are...micro-architecture, RTL design and functional verification * Experience with DFT and DFM flows Amazon is an equal opportunity… more
    Amazon (07/24/25)
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  • Sr . SOC Design - STA, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. ... signoff flow. * Work for Systems and Architecture, SoC Integration, Verification, DFT , Mixed Signal, IP owners, Synthesis, Place & Route and other local/remote… more
    Amazon (07/09/25)
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  • Senior Physical Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a ** Senior Physical Design Engineer ** to join the team. **Responsibilities** + Accountable ... for Design-for-Test ( DFT ) & Functional mode Timing Analysis and convergence within...(PD) domain. + Facilitate coordination across cross-functional teams, including DFT , RTL/Design/IP, Static Timing Analysis (STA), CAD, Architecture, Power… more
    Microsoft Corporation (08/08/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... teams, backend physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key Responsibilities:** + Responsible… more
    Cisco (07/22/25)
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  • Senior Product Test Engineer

    Cisco (San Jose, CA)
    Senior Product Test Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444763) + Location:San Jose, California, US + Area of InterestSupply Chain + ... in Silicon Operations, and with Cisco Systems NPI teams. Collaborate with DFT , Reliability, Quality, Failure Analysis and Manufacturing teams to resolve silicon… more
    Cisco (07/11/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If ... frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT /Test timing such as timing constraints, timing analysis, timing...to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift,… more
    NVIDIA (06/10/25)
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  • Senior Manufacturing Test Engineer

    CoStar Realty Information, Inc. (Sunnyvale, CA)
    Senior Manufacturing Test Engineer Job Description **CoStar Group** (NASDAQ: CSGP) is a leading global provider of commercial and residential real estate ... and operations to documentation, appraisal, and marketing. **About the Role:** The Sr . Manufacturing Test Engineer will be responsible for designing, developing,… more
    CoStar Realty Information, Inc. (07/12/25)
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  • Senior ASIC Synthesis Engineer

    NVIDIA (Santa Clara, CA)
    …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If ... You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL synthesis and gate level...power/area optimization across multiple design blocks + Work with DFT and Verification teams to ensure functional and timing… more
    NVIDIA (07/01/25)
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  • Senior ASIC Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... be doing: + Support the deployment of advanced Design-For-Test ( DFT ) and Automatic Test Pattern Generation (ATPG) solutions +...to stand out from the crowd: + Knowledge of DFT including fault models, ATPG, fault simulation, and diagnosis… more
    NVIDIA (07/26/25)
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