- BAE Systems (San Diego, CA)
- …hardware engineering intern to join our summer internship program for 2026. As an Hardware Engineer Technical Intern 3, you will join a team of engineers ... supporting hardware development opportunities that provide value to our customers...Education, Experience, & Skills** + Transitioning into Junior or Senior year during the Summer of 2026 + Majoring… more
- Celestica (San Diego, CA)
- …are that you're getting this information over at least one piece of hardware that we designed, developed, manufactured or service. Celestica is the brand behind ... you love in tech and we design, develop, and manufacture leading-edge Hardware Platform Solutions in Networking, Storage, and Server solutions from general purpose… more
- Amazon (Sunnyvale, CA)
- …Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior ASIC Design Engineer , you will be part of an advanced design and architecture ... In this role, you will: * Architect and Design world class imaging hardware * Communicate and work with team members across multiple disciplines * Develop… more
- NVIDIA (Santa Clara, CA)
- …GPUs and SOCs on standard FPGA prototyping platforms. We are now looking for a Senior FPGA Prototyping Engineer to join our Emulation team onsite in Santa Clara, ... high speed I/F such as USB4/3 is desirable + Prior experience with hardware emulation or prototyping (Synopsys HAPS, Zebu, Mentor Veloce, ProFPGA) of a… more
- NVIDIA (Santa Clara, CA)
- …with particular interest in algorithms and RTL Design. Understanding both Software and Hardware principles will be a key requirement for this role. What you'll be ... doing: + Architect, design, develop and support tools for RTL generation across all NVIDIA products + Architect automated workflows for supporting deliverables to multiple cross functional teams + Improve algorithms (in C++) for automated connectivity, auto… more
- NVIDIA (Santa Clara, CA)
- …We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer ! ... Someone who is excited to join a growing and multifaceted group of diverse individuals responsible for handling significant high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high… more
- NVIDIA (Santa Clara, CA)
- …Engineer ? If yes, We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and ... dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal circuit designs. What you'll be doing: + Performing physical layout for mixed-signal functions like PLL's, high speed SerDes, Analog to Digital converters, ESD… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by… more
- NVIDIA (Santa Clara, CA)
- …creativity and intelligence. We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing ... and dynamic group of diverse individuals responsible for contributing to our latest generation chiplet interface projects What you'll be doing: + Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking… more