• Sr . Principal Analog IC…

    Cadence Design Systems, Inc. (San Jose, CA)
    …make an impact on the world of technology. The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit ... of experience in CMOS SerDes or high-speed I/O IC design and development + Working knowledge of a set...requires proficiency in using CAD tools for circuit simulation, layout , and physical verification + Cadence tool experience, lab… more
    Cadence Design Systems, Inc. (07/04/25)
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  • Sr . Principal ASIC/Analog…

    Teledyne (Goleta, CA)
    …factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration ... a team that wins. **Job Description** The Integrated Circuit Design group at Teledyne FLIR develops the image sensors...level analysis. This also means working with digital and layout engineers to ensure the entire chip works as… more
    Teledyne (07/03/25)
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  • Principal OR Sr Principal

    Northrop Grumman (San Diego, CA)
    …an opening for a ** Principal Cybersecurity Systems Engineer** or ** Senior Principal Cybersecurity Systems Engineer** (CSSE) supporting the Triton program. ... and risk management. As a ** Principal Cybersecurity Systems Engineer** or ** Senior Principal Cybersecurity Systems Engineer** on this team, you will have… more
    Northrop Grumman (08/01/25)
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  • Sr . Principal Engineer Structural…

    Northrop Grumman (Palmdale, CA)
    …Aerospace Systems** located in **Palmdale, California** , has an opening for a ** Sr .** **Princi** **pal Structural Analysis Engineer** . This role is assigned to a ... load distribution, sizing, fittings/fasteners/joints/splices, acoustics/vibration familiarity, structural integrity plan, design criteria, stability, crippling, durability analysis and finite element… more
    Northrop Grumman (05/23/25)
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  • Senior Principal Analog…

    Northrop Grumman (Los Angeles, CA)
    …the successful transfer of an active DoD Secret Clearance.** **Basic Qualifications for a Senior Principal Analog Design Engineer:** + Bachelor's degree with ... design , modeling, and simulation + Experience with schematic capture and layout in Mentor Xpedition, Cadence, and/or Altium Designer + Experience with… more
    Northrop Grumman (06/28/25)
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  • Senior Principal Hardware…

    Cadence Design Systems, Inc. (San Jose, CA)
    …the leader in hardware emulation-acceleration technologies and products. Looking for a hands-on Principal HW Design Engineer who wants to expand their scope, and ... in our San Jose headquarter office, reports to the Sr Engineering Group Director of R&D, and works in...labs and datacenters. This position requires to do board design , schematic entry, work with layout engineers… more
    Cadence Design Systems, Inc. (07/25/25)
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  • Sr . Electrical Engineer - Water/Wastewater

    Parsons Corporation (Pasadena, CA)
    …9/80 Work Week or 40 hour work-week Parsons is seeking a ** Senior / Principal Electrical Engineer** to join our Water/Wastewater Design Engineering group based ... right now. We've got what you're looking for. **Job Description:** ** Senior / Principal Electrical Engineer - Water/Wastewater** **Location:** Pasadena, CA (Hybrid… more
    Parsons Corporation (06/14/25)
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  • Senior / Principal IC Design

    Insight Global (Milpitas, CA)
    …leading provider of high-performance analog and mixed-signal semiconductor solutions is looking for a Senior or Principal IC Design Engineer to join their ... applications. This is a hands-on technical role requiring strong circuit-level design experience and full IC tapeout ownership. Key Responsibilities: Design more
    Insight Global (08/08/25)
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  • Principal / Senior Principal

    Northrop Grumman (San Diego, CA)
    …requisition may be filled as a ** Principal Cyber Systems Engineer** or ** Senior Principal Cyber Systems Engineer** **Basic Qualifications for a Principal ... drive the built-in cybersecurity protections to the architecture and design . The CSSE also guides/supports the security layout...within six months of hire. **Basic Qualifications for a Senior Principal Cyber Systems Engineer** + Bachelor's… more
    Northrop Grumman (07/05/25)
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  • Principal Test Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …to product designs for test coverage and serviceability by participating in PRD, System Design , Diagnostic, Schematic and Layout Reviews + Design , develop ... capabilities to build our next-generation network firewalls. As a senior test engineer, you will be responsible for building...testing for PCBA and System level + Drive DfT ( Design for Testability) and functional test coverage analyses from… more
    Palo Alto Networks (07/05/25)
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