• Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …physical design, optimization, and ECO implementation eg cell sizing, buffering, vt swap . + Hands-on knowledge of industry standard Timing/STA EDA tools. + ... Proficiency in programming and scripting languages, such as TCL and Python. Ways to stand out from the crowd: + Experience with DFT timing closure for various modes eg scan shift, scan capture, transition faults, BIST, etc. + Knowledge of clocking and clock… more
    NVIDIA (06/10/25)
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