• Silicon ASIC Design Lead

    Google (Mountain View, CA)
    …etc. + Experience with methodologies for low power estimation, timing closure, synthesis . + Ability to drive multi-generational roadmap for IP/SoC development. Be ... You will collaborate with members of architecture, software, verification, power, timing, synthesis etc. to specify and deliver high quality RTL design. You will… more
    Google (08/08/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …verification plan development and verification. 3. Define timing constraints, run synthesis and static timing analysis. 4. Support the test program development, ... top level integration using automation tools. 10. Experience in RTL coding, synthesis and/or SoC Integration. 11. Experience in digital design Microrchitecture. 12.… more
    Meta (08/01/25)
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  • ASIC Design Engineer

    Broadcom (San Jose, CA)
    …implementation spec writing from marketing/system requirements, RTL design and verification, synthesis , static timing analysis. You will either be responsible for ... Must have good RTL experience including specification, design, verification, and synthesis . Must have strong UNIX-based EDA tool skills and knowledge of… more
    Broadcom (07/26/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …meet stringent power, performance, and timing goals. + Develop constraints, power intent, synthesis , and perform static checks such as: + LINT + CDC (Clock Domain ... Design, encompassing microarchitecture specification, RTL coding (Verilog/SystemVerilog), CDC/Lint closure, synthesis , timing constraints, PPA trade-offs, post-silicon debug, and successful… more
    Microsoft Corporation (07/25/25)
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  • Software Engineer II

    Cadence Design Systems, Inc. (San Jose, CA)
    …will be involved in developing a multi-threaded and distributed physical synthesis core engine in Innovus Implementation System. The position involves interaction ... troubleshooting and debugging software programs in the areas of physical synthesis . Work closely with product engineers/technical sales to provide engineering… more
    Cadence Design Systems, Inc. (07/19/25)
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  • Senior VLSI Design Engineering (New College Grad,…

    SanDisk (Milpitas, CA)
    …**Physical Design Engineering** - Physical Design Engineers will be responsible for logic synthesis , place and route (P&R), and timing analysis for NAND flash memory ... NAND Flash memory, with a focus on microarchitecture, RTL design, verification, logic synthesis , and static timing analysis. The goal is to deliver designs that meet… more
    SanDisk (07/19/25)
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  • Software Engineer II

    Cadence Design Systems, Inc. (San Jose, CA)
    …is a complete digital implementation product that encompasses physical design and logic synthesis . The product breadth means we are looking for skilled and motivated ... candidates with backgrounds in placement, routing, optimization, logic synthesis , extraction, static timing and power analysis. You will be part of a team… more
    Cadence Design Systems, Inc. (07/18/25)
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  • VLSI CAD Engineer, ECO Tools - New College Grad

    NVIDIA (Santa Clara, CA)
    …in-house algorithms for steps such as incremental CTS (clock tree synthesis ), incremental scan insertion, power hookup, placement, timing optimization, etc. + ... field) or equivalent experience. + Experience across VLSI, including exposure to synthesis , clocks, DFT, power distribution, timing, and place & route. + Proficiency… more
    NVIDIA (07/14/25)
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  • Sr. CAD Engineer, ASIC

    Amazon (Sunnyvale, CA)
    …verification methodology - Develop, regress and deploy digital implementation flows including Synthesis and Formal Verification - Enable digital design teams to meet ... verification methodology and debugging techniques - Familiar with basic Synthesis and Formal Verification methodology and flow development experience Preferred… more
    Amazon (07/10/25)
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  • ASIC Design Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis /timing clean design. + Support post-silicon validation activities. + Collaborate ... and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis , timing and back-end teams to accomplish your tasks. What we… more
    NVIDIA (07/10/25)
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