• Silicon Architect

    Meta (Sunnyvale, CA)
    …and drive chip level integration. 5. Supervise the RTL-to-GDS flow and assist with synthesis and timing closure to meet frequency, power and area goals. 6. Support ... transistor and circuit techniques 10. 2. Verilog or VHDL 11. 3. Logic design and synthesis 12. 4. Static Timing Analysis 13. 5. C, C++, Java, Ruby or Perl 14.… more
    Meta (08/01/25)
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  • SoC Physical Design Engineer

    Meta (Sunnyvale, CA)
    …blocks or full-chip designs, responsible for floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis and signoff 2. Collaborate with ... 10. Experience with low-power design techniques 11. Proficient in STA, clock tree synthesis and IR drop analysis 12. Knowledge of MBIST, Scan implementation and… more
    Meta (08/01/25)
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  • Distinguished Compiler Engineer - AI

    NVIDIA (Santa Clara, CA)
    …16+ years of relevant work or research experience in compiler optimizations, synthesis , super optimization and computer architecture. + Be able to work ... and compiler; Deep learning models and algorithms; Polyhedral methods; Program synthesis ; Tile based IR and domain specific language; Auto-tuning; Deep learning… more
    NVIDIA (08/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …fully verified design by working closely with verification engineers. + Deliver a synthesis /timing clean design while working with the physical design team to ensure ... deep understanding of ASIC design flow including RTL design, verification, logic synthesis , timing analysis, ECO, and post silicon debug. + Strong interpersonal… more
    NVIDIA (07/31/25)
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  • Marketing Manager, GSM - Jjmt - Neurovascular

    J&J Family of Companies (Irvine, CA)
    …and coordinate product launches . Identify appropriate market opportunities through synthesis of sound segmentation, targeting and positioning strategies and sales ... education plans to communicate product strategy to sales team . Synthesis of customer requirements through qualitative and quantitative market research methods… more
    J&J Family of Companies (07/29/25)
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  • Senior Researcher - CoreAI

    Microsoft Corporation (Sunnyvale, CA)
    …LLMs, SLMs, multimodal, or code-specific models. + Perform data curation and synthesis - Creating and refining datasets to optimize training outcomes. + Hands-on ... or code-specific models + 2+ years of expertise in data curation and synthesis , creating and refining datasets to optimize training outcomes + 2+ years of… more
    Microsoft Corporation (07/22/25)
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  • IC Physical Design Flow, Principal Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Digital Design Implementation & Signoff including Synthesis , Place and Route, Design Closure, and timing/power signoff + Guide customers ... Place & Route (Innovus, ICC2, Fusion Compiler) + Exposure and experience with Synthesis (Genus, RTL Compiler, Design Compiler) + Experience with EDA tools in the… more
    Cadence Design Systems, Inc. (07/18/25)
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  • Director of Cyclotron and Radiochemistry…

    UCLA Fielding School of Public Health (Los Angeles, CA)
    …PhD degree, preferably in chemistry, with excellent practical skills in radiochemical synthesis and methods, along with a broad understanding of organic chemistry ... and motivated to build a program + excellent practical skills in radiochemical synthesis and methods, along with a broad understanding of organic chemistry and… more
    UCLA Fielding School of Public Health (07/09/25)
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  • Software Architect - FPGA Emulation/Prototyping…

    Cadence Design Systems, Inc. (San Jose, CA)
    …guru + Experience working on delivery of EDA applications ( synthesis /place/route/timing/optimizations). + Expert in Timing & Clocking of Emulation & ... a plus + Working experience of EDA applications like synthesis /place/route/timing/optimizations + Excellent programming skills in C/C++, Object Oriented Programming,… more
    Cadence Design Systems, Inc. (07/09/25)
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  • Principal FPGA / Rtl Design Engineer

    Silvus Technologies (Irvine, CA)
    …blocks. * RTL coding, simulation, and test bench development. * FPGA synthesis and timing closure. * Hardware verification and troubleshooting; familiarity with ... * Proven expertise working with front-end RTL design tools, FPGA synthesis , timing closure, multiple clock-domain and/or high-utilization FPGA designs. * Experience… more
    Silvus Technologies (07/04/25)
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