• Design Verification Engineer

    Capgemini (Santa Clara, CA)
    Design Verification Engineer, contributing to the validation of advanced System -on- Chip (SoC) designs that integrate embedded CPUs and analog mixed-signal ... Develop test plans and coverage metrics from design specifications, and execute verification at both block and chip levels. + Automate environment setup and… more
    Capgemini (07/09/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification ... responsible for the verification closure of a design module or sub- system from test-planning, UVM... - SV Assertions, Formal, Emulation 17. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (07/22/25)
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  • ASIC Engineer, Design Verification

    Meta (Menlo Park, CA)
    …for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications.As a Design Verification ... responsible for the verification closure of a design module or sub- system from test-planning, UVM... like Mercurial(Hg), Git or SVN 12. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (07/11/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design ... responsible for the verification closure of a design module or sub- system from test-planning, UVM... like Mercurial(Hg), Git or SVN 20. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (06/25/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …the entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with ... the testing infrastructure to validate new core IP or System on Chip (SoC) implementations. You will...state of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with… more
    Meta (06/25/25)
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  • ASIC Engineer, Design Verification

    Meta (Sunnyvale, CA)
    …methodology or C/C++ based verification 16. 5. ASIC development cycles 17. 6. IP/sub- system or SoC ( System On Chip ) level verification 18. ... "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer, Design Verification Responsibilities: 1. Evaluate, develop and drive next generation… more
    Meta (07/11/25)
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  • Sr. Design Verification Manager,…

    Amazon (Cupertino, CA)
    …professional. Basic Qualifications - 8+ years of hands-on experience in ASIC/VLSI design verification , with a strong understanding of verification ... and Japan, and customers across all industries. Custom SoCs ( System on Chip ) live at the heart...Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers… more
    Amazon (05/17/25)
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  • Ethernet Design Verification

    Siemens (Fremont, CA)
    …of technology and physics to deliver better products in the Increasingly complex world of chip , board, and system design . About the Role We are seeking ... Architect with deep expertise in Ethernet technology and a strong focus on design verification . In this role, you will define and drive advanced verification more
    Siemens (07/24/25)
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  • Design Verification Engineer

    Amazon (San Diego, CA)
    verification , preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : ... correctness . Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM,… more
    Amazon (07/04/25)
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  • Senior Mixed Signal Design

    Capgemini (Santa Clara, CA)
    …and coverage metrics from design specifications, and execute both block- and chip -level tests. + Automate verification workflows using PERL and Python to ... **About the job you're considering** We're looking for a collaborative Senior Mixed-Signal Design Verification Engineer to help shape the future of SoC… more
    Capgemini (07/19/25)
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