• Senior Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design , synthesis/Lint/CDC/FEV and System on Chip (SOC) ... Engineer** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The...you will be interacting with various teams, including architecture, verification , and physical design , ensuring that the… more
    Microsoft Corporation (07/24/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …RTL coding in Verilog/ System Verilog or similar, PPA optimization, and design verification collaboration + Previous experience in the following: + ... team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to...Engineer** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The… more
    Microsoft Corporation (07/25/25)
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  • Sr. SOC Design - STA, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub- System STA and Signoff for a complex, multi-clock, multi-voltage ... STA, IR Drop aware STA) into SoC timing signoff flow. * Work for Systems and Architecture, SoC Integration, Verification , DFT, Mixed Signal, IP owners,… more
    Amazon (07/09/25)
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  • ASIC Design Engineer - Design

    Cisco (San Jose, CA)
    …the heart of silicon development at Cisco, you'll engage in every facet of chip design , from architecture to validation, using the latest silicon technologies to ... design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints… more
    Cisco (06/25/25)
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  • Digital Design Engineer

    Meta (San Diego, CA)
    …signal ICs to drive our industry leading virtual and augmented reality systems . **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will... of Computer Vision/Image Sensing IP. 2. Contribute to chip -level integration, verification plan development and … more
    Meta (06/13/25)
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  • Sr. DSP and Wireless Systems Engineer,…

    Amazon (San Diego, CA)
    …with RTL/RFIC designers, communication systems and software engineers to drive chip and system specifications . Develop and optimize HW/SW calibration ... communication SOCs that are used in Kuiper phased array systems . You will be implementing end-to-end system ...internal inter-disciplinary teams such as ASIC/RFIC designers, FW/SW engineers, design verification engineers. You will drive key… more
    Amazon (06/28/25)
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  • Manager, Digital Design - Mixed-Signal…

    NVIDIA (Santa Clara, CA)
    …and over 8 years of overall experience in mixed signal + Proven experience in mixed-signal chip design , with 3+ years in a leadership role + Expertise in Verilog ... roadmaps with business objectives + Establish and maintain standard methodologies for mixed-signal design and verification What we need to see: + MS or… more
    NVIDIA (06/10/25)
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  • Mechanical Product Design Engineer,…

    Google (Sunnyvale, CA)
    …As a key member of the team, you design and evaluate systems , identify product requirements, prepare system -related documentation and contribute to research ... technologies that power all of Google's services. As a Mechanical Engineer you design and evaluate our data center systems , identifying product requirements and… more
    Google (06/25/25)
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  • Technical Leader ASIC Design - Prototyping

    Cisco (San Jose, CA)
    …the heart of silicon development at Cisco, you'll engage in every facet of chip design , from architecture to validation, using the latest silicon technologies to ... gate SoCs to FPGAs. You will collaborate closely with Design , DV, and Software teams to understand chip...block or top-level IP integration + Collaborate with Software, Design , and Verification teams to validate the… more
    Cisco (06/25/25)
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  • Sr. Physical Design Engineer, Annapurna…

    Amazon (Cupertino, CA)
    …in the US, Europe, Singapore, and Japan, and customers across all industries. Custom SoCs ( System on Chip ) live at the heart of AWS Machine Learning servers. As ... power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification , ECO and sign-off - Develop physical design methodologies… more
    Amazon (06/04/25)
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