• CPU Server Physical Design Clock…

    Qualcomm (Santa Clara, CA)
    …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Physical Design Clock Engineer , you will work with microarchitecture, RTL ... design , CAD, block level and top level physical design teams to create best in class clocking solutions for next generation CPUs. **Minimum Skillsets** +… more
    Qualcomm (07/23/25)
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  • Design Implementation Engineer

    Qualcomm (San Diego, CA)
    …Engineering Group, Engineering Group > GPU ASICS Engineering **General Summary:** The Design Implementation Engineer will work in Qualcomm's Adreno GPU team ... and will be responsible for managing all aspect of front end implementation design challenges and methodology. As a member of the Graphics team, the successful… more
    Qualcomm (06/21/25)
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  • ASIC Design Efficiency Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Efficiency Engineer ! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... you'll be doing: + Develop innovative HW, GPU and system designs to extend the state of the art...of the art performance and efficiency. + Understand the design and implementation, develop methodology and infrastructure to drive… more
    NVIDIA (06/15/25)
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  • Senior Physical Design Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …the world of technology. Are you looking to re-enter the workforce as a Physical Design Application Engineer after taking a career break for caregiving? Who is ... and have a minimum of three years of Physical Design work experience. This role is not open to...modern life depends on. We are a global electronic design automation (EDA) company, providing software, hardware, and intellectual… more
    Cadence Design Systems, Inc. (07/02/25)
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  • CPU Physical Design Timing Engineer

    Qualcomm (San Diego, CA)
    …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... correlation. + Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions. + Evaluate multiple timing… more
    Qualcomm (06/10/25)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …manage and optimize the Cloud infrastructure. We are looking for a **Senior Design Verification Engineer ** to join the team. **Responsibilities** + Establish ... yourself as an integral member of a design verification team for the development of AI components...with a delivering complex Application Specific Integrated Circuits(ASIC) or System on Chip(SOC). **Other requirements:** Ability to meet Microsoft,… more
    Microsoft Corporation (08/08/25)
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  • Senior Design Verification Engineer

    Amazon (Sunnyvale, CA)
    …tablets, Fire TV and Amazon Echo. What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will be part of an advanced engineering and ... Deliver detailed test plans for verification of complex digital design blocks by working with design engineers...at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting… more
    Amazon (06/25/25)
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  • FPGA Design /Verification Engineer

    Butler America (Sunnyvale, CA)
    FPGA Design /Verification Engineer Location: Sunnyvale, CA Job ID: #71390 Pay Range: $75-90 The selected candidate will be responsible for ASIC & FPGA development ... on R&D program. This engineer with have experience in developing, testing, and integrating...and integrating digital signal processing (DSP), high speed digital design , high speed communication and system -on-chip (SOC)… more
    Butler America (08/08/25)
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  • ASIC Design Verification Engineer

    Cisco (San Jose, CA)
    ASIC Design Verification Engineer , Technical Leader Apply (https://jobs.cisco.com/jobs/Login?projectId=1447177) + Location:San Jose, California, US + Area of ... in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA....8 years of relevant experience required; prior experience with System Verilog and UVM methodology + Prior experience in… more
    Cisco (07/19/25)
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  • Design Verification Engineer

    Arrow Electronics (Sunnyvale, CA)
    **Position:** Design Verification Engineer (eInfochips Inc) **Job Description:** **Role: Design Verification Engineer ** **Location: Sunnyvale CA (Hybrid ... Be Doing:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least 8+ year...a leading global provider of product engineering and semiconductor design services. A rich history of over two decades,… more
    Arrow Electronics (06/11/25)
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