• Product Engineering Intern - Genus Synthesis…

    Cadence Design Systems, Inc. (San Jose, CA)
    …team to evaluate and improve Genus, a logic synthesis tool used to optimize Power , Performance , and Area (PPA) for advanced digital ASICs. + Analyze and ... validate new features within Genus, ensuring correctness and identifying optimal configurations. + Explore and address challenges in physically aware synthesis, bridging the gap between logic synthesis and place & route. + Support internal teams and customers… more
    Cadence Design Systems, Inc. (10/29/25)
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  • Senior Power Systems Engineer

    Arup (Oakland, CA)
    …for over 75 years, guiding how we shape a better world. We are seeking a **Senior** ** Power Systems Engineer** to join our West Geography as a part of the Energy ... Engineering and Power Systems (EEPS) Team. This role will...specifications, and construction-ready drawings. + Perform energy production estimates, system performance modeling, and techno-economic evaluations +… more
    Arup (12/10/25)
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  • AR/VR Silicon Architect

    Meta (Sunnyvale, CA)
    system solution 12. Experience in evaluating architectural tradeoffs in speed, performance , power , area 13. Experience in employing scientific methods to ... **Summary:** Meta's mission is to give people the power to build community and bring the world...including selecting ASIC technologies, FPGA ASIC emulation, and other system topics such as interface approaches, etc 6. Support… more
    Meta (10/11/25)
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  • Senior Hardware Engineer, Geo

    Google (Mountain View, CA)
    …. In this role, you will work with internal and external teams to define system requirements, design image capture and embedded systems boards to collect and ... + Apply standard procedures to improve constrained hardware components to meet performance , power , and cost-effectiveness requirements. + Drive efforts for the… more
    Google (12/11/25)
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  • Hardware Engineer, Input Sensing

    Google (Mountain View, CA)
    …identify and customize the design solution based on trade-offs in packaging, performance , power or technology selection, and scope hardware project. Collaborate ... practices to optimize complex or constrained hardware components to meet performance , power , and cost-effectiveness requirements. Accurately predict consequences… more
    Google (11/18/25)
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  • Senior ASIC Design Engineer, Hardware Compute…

    Amazon (Sunnyvale, CA)
    …micro-architecture from architecture guidelines and model analysis. - Experience in performance / power /area analysis and trade-offs - Proficient in design ... variety of low power design techniques - Working experience with high performance industry standard buses like AMBA AXI4 - Experience in integrating third party… more
    Amazon (12/12/25)
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  • Senior Deep Learning Systems Engineer,…

    NVIDIA (Santa Clara, CA)
    …of a Deep Learning Systems Engineer would be to analyze the performance and power consumption of deep learning applications on datacenter-class hardware and ... future of AI? Do you have an interest in system architecture and performance ? In this role...performance metrics of DL workloads running on Nvidia systems . + Analyze system and software characteristics… more
    NVIDIA (10/22/25)
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  • Advanced Device Modeling Expert - TCAD

    Applied Materials (Santa Clara, CA)
    …the continuous demands for scaled devices, denser interconnects that significantly improves the system Power , Performance and Area (PPA). We are looking ... We are working on exciting projects, connecting materials to systems , to drive new innovations that enable a wide...and sensitivity analyses to understand key drivers of electrical performance and reliability. + Contribute to the development and… more
    Applied Materials (10/21/25)
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  • Principal Validation Engineer

    Microsoft Corporation (Mountain View, CA)
    …the following validation domains : functional, electrical, high speed interfaces, memory, power / performance , debug/BU and tool development. You will be part of ... are responsible for delivering cutting-edge AI designs that can perform complex and high- performance functions in an extremely efficient manner. We are looking for a… more
    Microsoft Corporation (12/14/25)
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  • Principal Design Engineer

    Microsoft Corporation (Mountain View, CA)
    …Circuits (ASIC)/SOC designs. + 5+ years of experience in Synthesis, Timing constraints, Power , Performance , Area (PPA) trade-offs and Post-Silicon Debug + 5+ ... Engineer to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC) Silicon team. The candidate must...of the design team driving many facets of high performance , high bandwidth designs. The tasks will include working… more
    Microsoft Corporation (12/14/25)
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