- NVIDIA (Santa Clara, CA)
- …algorithms, programming models and applications + Evaluate PPA ( performance , power , area) for hardware features and system level architectural trade-offs. ... in deep learning performance and efficiency + Analyze performance , cost and power trade-offs by developing analytical models, simulators and test suites +… more
- Amazon (Cupertino, CA)
- …you will be responsible for the architecture, design, deployment, of the Power Sub- system of next generation servers and systems including AC/DC power ... We are seeking experienced hardware design engineers to architect and design power sub- systems for next-generation servers and AWS specific hardware components.… more
- Google (Mountain View, CA)
- …shared caches, and optimizations with other parts of the CPU to deliver the best Power Performance Area (PPA). Google is proud to be an equal opportunity ... design specification to productization, including integration into the goal-oriented System on a Chips (SoC). You will lead and...and deciding on the best design options with complexity, performance , power and area and schedule in… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Takes technical lead on wide range of projects. Ability to understand high-speed, high- performance signal and power integrity related issues, and work with peers ... the context of multiple flows including high speed signal and/or power design, signal and power integrity. Design experience and industry knowledge of Signal, … more
- NVIDIA (Santa Clara, CA)
- …simulator and analysis tools in C++/Python. + Evaluate PPA ( performance , power , area) for hardware features and system -level architectural trade-offs. + Work ... We are now looking for a Senior Deep Learning Performance Architect! NVIDIA is seeking outstanding Performance ...Learning Performance Architect! NVIDIA is seeking outstanding Performance Analysis Architects to help analyze and develop the… more
- SanDisk (Milpitas, CA)
- …route (P&R), and timing analysis for NAND flash memory chips, ensuring designs meet performance , power , and area (PPA) targets. Engineers in this role will work ... The goal is to deliver designs that meet target power , performance , and area objectives. As a...analog/mixed-signal and digital + Experience with HSPICE, FINESIM, VERILOG, System Verilog, and RTL design + Proficiency in troubleshooting,… more
- NVIDIA (Santa Clara, CA)
- … metrics and drive power reductions + Execute and deliver fully verified, high performance , area and power efficient RTL to achieve design targets + You will ... We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power...you'll be doing: + Develop innovative HW, GPU and system designs to extend the state of the art… more
- NVIDIA (Santa Clara, CA)
- …your programming background to manage & manipulate complex datasets to assess performance , power , yield, and quality improvements for NVIDIA's family of ... improve the data modelling infrastructure and test procedures. + Identify performance and power -limiting constraints and drive product-specific customizations.… more
- Meta (Sunnyvale, CA)
- …& Integration Engineer 12. Experience with RTL Synthesis and design optimization for Power , Performance , Area 13. Knowledge of front-end and back-end ASIC tools ... Lint, CDC analysis, timing constraints, synthesis to build efficient System on Chip (SoC) and IP for data center...and generate optimized Gate Level Netlist for Timing, Area, Power 2. Debug the timing/area/congestion issues and work with… more
- Amazon (Sunnyvale, CA)
- …in RTL coding (Verilog/ System Verilog) and debug, as well as performance / power /area analysis and trade-offs - Experience in closing full-chip and subsystem ... computer vision and robotics. You will work closely with System Architects, SoC architects, IP developers and physical design...physical design teams to develop SoCs that meets the power , performance and area goals for Amazon… more