• Staff Platform System Architect, AI/ML,…

    Google (San Diego, CA)
    …with an emphasis on computer architecture. + Experience optimizing software and systems for power , thermal, and memory footprint constraints. + Experience ... expertise will shape the next generation of hardware experiences, delivering unparalleled performance , efficiency, and integration. As a Staff System Architect,… more
    Google (07/10/25)
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  • Analog Circuit Design Engineer

    Amazon (San Diego, CA)
    …will be on creating power and cost optimized solutions for a given system performance . Export Control Requirement: Due to applicable export control laws and ... Key job responsibilities Explore architectures for high performance analog sub- systems and make detailed presentations on power /area/ performance more
    Amazon (08/11/25)
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  • System Level Testability Engineer

    NVIDIA (Santa Clara, CA)
    …needed to support manufacturing screens effectively. + Prototype and fine-tune speed, power , performance , yield, and quality on pre-production silicon + Measure ... NVIDIA Silicon Solutions Group is now looking for a System Level Testability Engineer to be part of the...key performance indicators used to evaluate the effectiveness of the… more
    NVIDIA (06/13/25)
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  • Senior Hardware Engineer - Micro-Architect

    quadric.io, Inc (Burlingame, CA)
    …wide variety of edge and endpoint devices, ranging from battery operated smart-sensor systems to high- performance automotive or autonomous vehicle systems . ... & RTL implementation of the processor in SystemC or SystemVerilog + Own Power , Performance & Area (PPA) optimization + Contribute to timing closure through full… more
    quadric.io, Inc (06/09/25)
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  • Principal Optical System Architect

    TE Connectivity (CA)
    …of high-speed electrical, optical, and hybrid interconnect solutions, balancing performance , power , latency, cost, and manufacturability. + Collaborate ... Principal Optical System Architect At TE, you will unleash your...+ Define novel, scalable CPO/NPO architectures to meet future performance , power , and density demands of AI,… more
    TE Connectivity (07/09/25)
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  • Electrical Engineer

    Leidos (Ridgecrest, CA)
    …the research, design, development, integration, production, fielding, and sustainment of high- power , high- performance RF integrated radar simulators (and other ... in the loop, remotely operated, open architecture, modular designs. + Leads system -level design and development of integrated electronic systems including… more
    Leidos (08/13/25)
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  • Virtual Platform Hardware Modeling Engineer

    Meta (Sunnyvale, CA)
    …metrics, allowing for data-driven design decisions and trade-off analysis to optimize system performance and power consumption **Minimum Qualifications:** ... and Virtual Reality (VR) devices and platforms. The compute performance and power efficiency requirements of these...5. Enhance the virtual platforms to enable SoC and system architecture exploration by instrumenting models for power more
    Meta (08/13/25)
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  • ASIC Engineer, Physical Design

    Meta (Sunnyvale, CA)
    …with experience in physical design from RTL to GDSII in low power and high- performance designs to build efficient System on Chip (SoC) and IP for data center ... end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs 5. Interface with the RTL design team to drive design… more
    Meta (08/07/25)
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  • Silicon ASIC Design Lead

    Google (Mountain View, CA)
    …low power design methodology and evaluate design options with complexity, performance , power and area in mind. Google's mission is to organize ... diagram, data flow, pipelines, etc. + Oversee RTL development, debug functional/ performance simulations . + Participate in synthesis, timing/ power estimation… more
    Google (08/08/25)
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  • ASIC Design Manager, TPU Compute

    Google (Sunnyvale, CA)
    …Integration, from early architecture phase through tapeout. + Knowledge of high performance and low- power design techniques. + Knowledge of ASIC Verification, ... Tensor Processing Unit (TPU) Compute, you will develop high performance and low power hardware to enable...understand and implement the design requirements for clocking and power management. The ML, Systems , and Cloud… more
    Google (08/08/25)
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