• Hardware Engineer II (Co-op) - United States

    Cisco (San Jose, CA)
    …design for reliability or manufacturability. + Familiarity with high-speed signal integrity , power electronics, or embedded system design. + Knowledge ... from the lowest levels of circuit design to large system design and see your contribution all the way...Layout + Hardware Automation + Validation and Test + Signal Integrity + Power Design… more
    Cisco (11/14/25)
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  • Hardware Engineer, Platforms, University Graduate

    Google (Sunnyvale, CA)
    …are met with our systems and cross-functional design teams (eg, Mechanical, Thermal, Power , Signal Integrity etc.) to design the desired product. You ... schematic capture and PCB layout, and layout practices for signal integrity , power delivery, and...system design team, you will work on hardware systems projects to craft solutions for current and future… more
    Google (09/26/25)
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  • Hardware Signal Integrity Test…

    Google (Sunnyvale, CA)
    Hardware Signal Integrity Test Engineer, Platforms, University Graduate _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Early** Experience completing work ... generator) + Experience with Linux or other Unix operating systems (eg, Ubuntu or RHEL) and shell scripts. +...+ Proficiency in one or more disciplines related to signal integrity measurements, hardware test, hardware qualification.… more
    Google (09/26/25)
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  • Senior Manager, Silicon Product and Test…

    Google (Sunnyvale, CA)
    …high performance IC test and characterization flows for PVT, signal and power integrity characterization, System correlation, and participate in silicon ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...focus on TPU architecture and its integration within AI/ML-driven systems . As a Technical Lead Manager, you will build… more
    Google (11/25/25)
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  • Design Engineering Director

    Cadence Design Systems, Inc. (San Jose, CA)
    …Schematic and layout level. Familiarity with peripheral chips, high speed interface design techniques, Signal and Power integrity checks / analysis and fixes ... (with BTech) or 10 years (with MTech) experience in Post-Silicon PHY, Systems Interop and Compliance testing. * 2-3 years of management experience leading/mentoring… more
    Cadence Design Systems, Inc. (10/07/25)
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  • Principal Optical System Architect

    TE Connectivity (CA)
    …thermal, and mechanical domains. + Conduct end-to-end simulations and modeling to optimize signal integrity , power efficiency, and thermal performance. + ... Principal Optical System Architect Posting Start Date: 7/8/25 Job Description:...high-speed electrical, optical, and hybrid interconnect solutions, balancing performance, power , latency, cost, and manufacturability. + Collaborate with internal… more
    TE Connectivity (11/27/25)
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  • Electrical Engineer, Spectacles, L5

    Snap Inc. (Palo Alto, CA)
    …and Rigid Flex designs + Debug hardware issues with cross-functional teams such as desense, power states, signal integrity , ESD and EMI + Analyze circuit ... range + Test and validate all board level and systems level aspects of electrical designs + Collaborate closely...switching power supply circuits, EMI mitigation, high-speed signal integrity and power delivery… more
    Snap Inc. (11/22/25)
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  • Electrical Design Engineer

    Capgemini (Santa Clara, CA)
    …and PCB layout tools such as Altium, Cadence, or OrCAD. + Solid understanding of signal integrity , power integrity , and thermal management. + Hands-on ... where you'll contribute to the design, development, and optimization of mission-critical systems used by global enterprises. **Your Role** + Provide ongoing support… more
    Capgemini (11/11/25)
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  • Principal FPGA Electrical Engineer

    Oracle (Santa Clara, CA)
    …smaller organization within Oracle to team up with other technical experts in Signal Integrity , Power , Electrical, Validation, Mechanical, Diagnostics, BIOS ... to work with our FPGA, electrical, mechanical, SI and power teams in Santa Clara, California!_ _Here is your...based on the latest high-end server-grade merchant silicon._** _The systems delivered are integrated as building blocks for some… more
    Oracle (11/25/25)
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  • High Speed SerDes DSP RTL Designer

    Broadcom (San Jose, CA)
    …micro architecture with standard peripherals such as AMBA BUS/I2C/SPI/UART.** + **Deep understanding of Signal Integrity and Power Integrity modeling for ... in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/ System Verilog coding for PAM4 DSP based SerDes including equalization, adaptation and… more
    Broadcom (11/11/25)
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