• Senior ASIC Design Verification…

    Google (Sunnyvale, CA)
    …AI (MSCA) organization at Google designs, implements, and manages the hardware, software , machine learning, and systems infrastructure for all Google services ... SystemVerilog for ASICs. + Experience in memory subsystem design verification . + Experience in Power aware verification ,...bring-up. + Familiarity with ASIC standard interfaces and memory system architecture. In this role, you'll work to shape… more
    Google (04/25/25)
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  • Senior ASIC Verification Engineer…

    NVIDIA (Santa Clara, CA)
    …verify the world's leading GPUs. In this role, you will be doing unit level verification of the process scheduling and system interface hardware of the GPU. This ... position will be working across many NVIDIA teams from software , to architecture, design, methodology, and more. The GPU...the design are verifiable + Architect and plan the verification strategy and execution for sub- system features… more
    NVIDIA (04/11/25)
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  • ASIC Design Verification Principal…

    Palo Alto Networks (Santa Clara, CA)
    …to create an environment where we all win with precision. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in ... emulation, and silicon validation. **Your Impact** + Collaborate with engineers in software , architecture, design, and verification teams to create comprehensive… more
    Palo Alto Networks (04/04/25)
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  • MLA IP Design Verification Engineer…

    Amazon (Cupertino, CA)
    …in the future. Basic Qualifications - BS in engineering - 5+ years of design verification experience using System Verilog and UVM - 5+ years in testbench ... levels of logic including: IP blocks and full SOC system testing - Experience with C/C++, Python, or Perl...multiple verification platforms - Experience with formal verification - Experience with embedded software -… more
    Amazon (03/19/25)
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  • Physical Verification and Convergence…

    Google (Sunnyvale, CA)
    …AI (MSCA) organization at Google designs, implements, and manages the hardware, software , machine learning, and systems infrastructure for all Google services ... equivalent practical experience. + 3 years of experience in physical design, verification , and various methodologies. + Experience in Python, Tcl, or Perl scripting.… more
    Google (04/17/25)
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  • Senior ASIC Verification Engineer

    Tarana Wireless (Milpitas, CA)
    …What you'll be doing: + Work with some of the best DSP, system , and software engineers to define verification strategies and execute plans at system or ... full chip level + Build and continuously improve verification infrastructure and methodologies to meet the demands of...the demands of next generation SoCs + Work with system architects, RTL designers, FPGA and emulation engineers to… more
    Tarana Wireless (04/13/25)
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  • CPU Functional Verification Engineer…

    Google (Mountain View, CA)
    …a related field, or equivalent practical experience. + Experience with verification methodologies and languages such as UVM or SystemVerilog. Preferred ... an emphasis on computer architecture. + Experience in low-power design verification . + Experience with Universal Verification Methodology (UVM), SystemVerilog,… more
    Google (04/29/25)
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  • CPU Formal Verification Engineer

    Qualcomm (Santa Clara, CA)
    …team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next ... join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the...experience in application of formal methods in hardware or software + Strong model checking or theorem proving background/experience… more
    Qualcomm (04/01/25)
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  • Senior ASIC Design Verification…

    Cisco (San Jose, CA)
    …design, and post-silicon validation The team comprises micro-architects, front-end designers, and verification engineers. Cisco is a system company, so you can ... also use the ASIC to work with the System and Software teams and participate in...System Verilog/UVM. * Experience with ASIC design and verification processes, debugging, methodology, and tools. * Experience in… more
    Cisco (03/05/25)
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  • Design Verification Engineer

    Amazon (Cupertino, CA)
    …- BS Degree or Higher in EE or CS or CE. - 3+ years of design verification experience using System Verilog and UVM - 3+ years of experience in testbench ... Experience verifying multiple levels of logic including: IP blocks and full SOC system testing. - Experience using multiple verification platforms. - Experience… more
    Amazon (04/27/25)
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