- Google (Mountain View, CA)
- …+ bonus + equity + benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is determined by work location and ... additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details… more
- Google (San Diego, CA)
- …+ bonus + equity + benefits. Our salary ranges are determined by role, level , and location. Within the range, individual pay is determined by work location and ... additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details… more
- SanDisk (Milpitas, CA)
- …of data observability features and tools for validation purpose + Perform system- level verification tests of NAND management FW features + Perform end-of-life (EOL) ... reliability verification tests + Perform failure analysis on EOL and other FW maturity test failures + Data analysis based on drive logs and statistical data * Collaborate with FW and other design teams on design feedback and improvement * Present data report… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …and/or emulation platform is a plus. + Firmware development of embedded microcontroller systems is a plus. Substantial experience with Verilog is required, as are ... and compensation may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include: paid vacation and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale ... and compensation may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include: paid vacation and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …products . Strong CS fundamentals background in data structures, algorithms, systems architecture are required. Minimum Qualifications: Minimum years of industry ... and compensation may vary based on factors such as qualifications, skill level , competencies and work location. Our benefits programs include: paid vacation and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …engineering team working on Power Noise Reliability analysis platform within Multiphysics Systems BU at Cadence.* Build domain expertise in power integrity , 3DIC ... out the critical issues from trivial ones.* Ability to solve interface level problems emanating from IC Implementation side and System analysis side.* Ability… more
- Lockheed Martin (Palmdale, CA)
- …span the avionics services\. Integration activities will include a multitude of host systems , such as live assets of varying capability and structure simulated ... systems , and laboratory environments that include constructive simulations, physical...and system simulations\. Perform other duties as assigned\. A level 3 employee **Typically has 5 \- 10 years**… more
- SpaceX (Hawthorne, CA)
- …remote work will not be considered COMPENSATION AND BENEFITS: Pay range: Security Engineer / Level I: $130,000.00 - $150,000.00/per year Security Engineer / ... Security Engineer (Identity and Access Management) Hawthorne, CA Apply...we must protect the confidentiality, integrity, and availability of systems and processes across the enterprise. As a highly… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …team creating technologies and products that enable static and dynamic transistor level analysis of the most advanced custom digital and mixed-signal circuits built ... of EDA tools and one or more of transistor level timing, power, noise, aging, reliability, and emir analysis...engineering principles + Proficiency in analyzing transistor or gate level schematics + The preferred candidate is expected to… more