• ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... Chip (SoC) for data center applications. As a Design Verification Engineer , you will be part of... like Mercurial(Hg), Git or SVN 20. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (08/01/25)
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  • ASIC Engineer , Design Verification

    Meta (Menlo Park, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of... - SV Assertions, Formal, Emulation 17. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (08/01/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design ... On Chip (SoC) for data center applications.As a Design Verification Engineer , you will be part of... like Mercurial(Hg), Git or SVN 12. Experience with verification of ARM/RISC-V based sub- systems or SoCs… more
    Meta (08/01/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
    Meta (08/01/25)
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  • Verification & Validation System…

    Actalent (Los Angeles, CA)
    Job Title: Verification & Validation System EngineerJob Description The Verification & Validation System Engineer will delve deeply into component and ... system-level and network-level operations from concept through execution. Additionally, the engineer will integrate and perform verification of the end-to-end… more
    Actalent (08/02/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with an ... of the art IPs or SoCs. **Required Skills:** Design Verification Engineer Responsibilities: 1. Work with researchers...AI/ML and Networking designs 16. Experience with revision control systems like Mercurial(Hg), Git or SVN 17. Master's degree… more
    Meta (08/01/25)
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  • Senior ASIC Design Verification

    Qualcomm (San Diego, CA)
    …that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate ... to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design, optimize, verify, and test… more
    Qualcomm (06/12/25)
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  • ASIC FPGA Design and Verification

    The Boeing Company (Mountain View, CA)
    …of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems ). As an ASIC/FPGA Engineer on the Boeing Electronic Products ... professional growth. Find your future with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and … more
    The Boeing Company (07/26/25)
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  • Senior Design Verification Engineer

    Amazon (Sunnyvale, CA)
    …is powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are ... this role, you will be responsible for defining the verification methodology and implementing the corresponding test plan for... methodology and implementing the corresponding test plan for sub- systems and the full chip. You will participate in… more
    Amazon (08/10/25)
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  • Silicon Engineer , Design…

    Google (Goleta, CA)
    …or equivalent practical experience. + 5 years of experience with design verification . + Experience verifying digital systems using SystemVerilog/UVM. + ... and building mixed-mode models for end-to-end DV coverage. + Experience with verification strategy definition, verification planning, coverage closure and UVM… more
    Google (08/08/25)
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