• Mechanical Design Verification

    Meta (Sunnyvale, CA)
    …new technology introduction, product launch and post-launch testing. As a Design Verification Engineer , you will require working closely with a wide ... drive test execution and data collection. **Required Skills:** Mechanical Design Verification Engineer Responsibilities: 1. Define mechanical verification more
    Meta (12/20/25)
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  • ASIC/FPGA Verification Engineer

    The Boeing Company (El Segundo, CA)
    …parts of Boeing (AvionX; Missiles & Weapons; Strike, Surveillance and Mobility; and Autonomous Systems ). As an ASIC/FPGA Verification Engineer on the Boeing ... & Weapons Systems has an exciting opportunity for multiple **ASIC/FPGA Verification Engineers (Associate, Experienced, or Lead)** to join us as part of our… more
    The Boeing Company (12/25/25)
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  • ASIC Design Verification Engineer

    Google (Sunnyvale, CA)
    …architecture and its integration within AI/ML-driven systems . As an ASIC Design Verification Engineer , you will use design and verification expertise to ... ASIC Design Verification Engineer , Machine Learning _corporate_fare_ Google...for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. The US base salary… more
    Google (12/16/25)
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  • Formal Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now seeking a Formal Verification Engineer , focusing on the firmware verification ! In this role, you will be instrumental in ensuring the correctness, ... co- verification challenges at scale. As a Formal Verification Engineer , your primary responsibility will be...plus). + 3+ years of relevant experience in formal verification of hardware, software, or embedded systems .… more
    NVIDIA (12/22/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement ... verification plans, and build test benches for block, IP, sub-system, and SoC level verification 2. Develop functional tests based on verification test… more
    Meta (12/20/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC ... verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop functional tests based on verification more
    Meta (12/20/25)
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  • Senior Physical Verification

    NVIDIA (Santa Clara, CA)
    …impact on the world! We are currently looking for a Sr VLSI Physical Verification Methodology Engineer . What you'll be doing: + Responsible for support and ... Integrate new workflows and checks into larger workflow automation systems . + Participate in developing physical verification ...salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for… more
    NVIDIA (11/04/25)
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  • Senior Engineer - Deep Learning Compiler…

    NVIDIA (Santa Clara, CA)
    …technologies to accelerate deep learning workloads. We are looking for an engineer to implement compiler verification software & related infrastructure in ... critical problems working alongside a diverse set of minds in GPU computing and systems software, doing what you enjoy. If this sounds like a fun challenge, we… more
    NVIDIA (12/22/25)
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  • Senior Verification Engineer

    Microsoft Corporation (Mountain View, CA)
    …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... for multiple IPs, SoCs or systems . + 2+ years of experience leading pre-silicon verification of blocks and sub systems through full cycle + 2+ years of… more
    Microsoft Corporation (12/17/25)
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  • Verification Engineer

    Broadcom (San Jose, CA)
    …driving verification closure * Hands on experience in CDC check, formal verification , functional coverage, gate level debug and emulation tools * Very strong ... chips. This position is responsible for IP and subsystem verification , including SerDes and processor subsystem among many other...* Proven expertise in defining block and sub-system level test plans, creating reusable test benches, and… more
    Broadcom (10/30/25)
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