- Meta (Sunnyvale, CA)
- …transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement IP/SoC ... verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop functional tests based on verification … more
- NVIDIA (Santa Clara, CA)
- …impact on the world! We are currently looking for a Sr VLSI Physical Verification Methodology Engineer . What you'll be doing: + Responsible for support and ... Integrate new workflows and checks into larger workflow automation systems . + Participate in developing physical verification ...salary range is 136,000 USD - 212,750 USD for Level 3, and 168,000 USD - 264,500 USD for… more
- NVIDIA (Santa Clara, CA)
- …technologies to accelerate deep learning workloads. We are looking for an engineer to implement compiler verification software & related infrastructure in ... critical problems working alongside a diverse set of minds in GPU computing and systems software, doing what you enjoy. If this sounds like a fun challenge, we… more
- Microsoft Corporation (Mountain View, CA)
- …will manage and optimize the Cloud infrastructure. We are looking for a **Senior Verification Engineer ** to join the team. **Responsibilities** The role will be ... for multiple IPs, SoCs or systems . + 2+ years of experience leading pre-silicon verification of blocks and sub systems through full cycle + 2+ years of… more
- Broadcom (San Jose, CA)
- …driving verification closure * Hands on experience in CDC check, formal verification , functional coverage, gate level debug and emulation tools * Very strong ... chips. This position is responsible for IP and subsystem verification , including SerDes and processor subsystem among many other...* Proven expertise in defining block and sub-system level test plans, creating reusable test benches, and… more
- Insight Global (Irvine, CA)
- …wearable insulin-delivery systems . They are looking for a hands-on Design Verification Lead to drive verification activities for their patch-pump program and ... reflect design intent. This is a highly visible, high-impact position for an engineer who thrives in regulated environments and enjoys both leading and being… more
- Amazon (Sunnyvale, CA)
- …with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C . ... or related field, or equivalent experience - 7+ years in verification preferably in communication systems - 3+ years in UVM, C, and scripting Preferred… more
- Amazon (San Diego, CA)
- …with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C . ... progress to the program . Understand and debug system level communication scenarios on pre silicon and post silicon...System C, and scripting experience - 7+ years in verification preferably in communication systems Preferred Qualifications… more
- Amazon (Cupertino, CA)
- …and Japan, and customers across all industries. We are seeking experienced Design Verification Engineers to build the next generation of our cloud server chips. Our ... responsibilities - verify custom chip designs at the SOC level - integrate 3rd party IPs and VIPs into...or CS or CE. - 8+ years of design verification experience using System Verilog and UVM - 8+… more
- Northrop Grumman (El Segundo, CA)
- …not only part of history, they're making history. **We have an opening for either a Systems Engineer or Principal Systems Engineer to join our Phoenix ... at a higher grade based on qualifications listed below._ **Basic Qualifications:** + ** Systems Engineer :** 2 years of relevant experience with a Bachelor's in… more