- The Boeing Company (Mountain View, CA)
- …and complexity + Validate design through hardware integration test with special test equipment, test -beds, and higher- level systems as needed + Train ... Surveillance and Mobility; and Autonomous Systems). As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will...where we're hiring design and verification engineers at every level as we're only limited by our bandwidth for… more
- Microsoft Corporation (Mountain View, CA)
- …Engineering (CHIE) team is seeking a highly motivated Principal Hardware Systems Validation Engineer to work in a team of other hardware and software developers to ... engineering functions. Responsibilities will include architecting and developing efficient test and debug frameworks for cutting edge technologies, building … more
- Teradyne (San Jose, CA)
- We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, ... Teradyne's test technology ensures your device works right the first...are seeking a highly capable and cross-functional Factory Application Engineer with a strong foundation in computer programming, electrical… more
- Amazon (San Diego, CA)
- …third party suppliers to drive product definition, design, optimization, implementation, and test . The Senior Hardware Engineer will have a complete ... A day in the life: As an Senior Hardware Engineer , you will have the opportunity to work on...Optimize PCB stack-up for performance and cost - Generate test plans/procedures based off high level requirement… more
- Meta (Sunnyvale, CA)
- …and track detailed test plans for the different modules and top level systems. Validation coverage includes SoC, low speed signal interface (I2C, I2S, PDM etc), ... **Summary:** Electrical Design Validation Engineer in Wearables Hardware will be an integral...substantial aspect of design verification & validation, and design test protocols with line-of-sight to mass production. Our team… more
- The County of Los Angeles (Los Angeles, CA)
- …refrigeration equipment and auxiliaries, one (1) year of which must have been at the level of Stationary Engineer II.* LICENSE: A valid California Class C Driver ... Suite programs. SPECIAL REQUIREMENT INFORMATION : *Experience at the level of Stationary Engineer II is defined...notifications to be a valid reason for a late test administration, re-scheduling, or extension of appeal rights period.… more
- Meta (Sunnyvale, CA)
- …Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Meta (Sunnyvale, CA)
- …and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification 2. Develop ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Meta (Sacramento, CA)
- …Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Meta (Sunnyvale, CA)
- …Responsibilities: 1. Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2. Develop ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more