- Qualcomm (Santa Clara, CA)
- …fundamentals in digital ASIC design; experience using Verilog or VHDL + Experience with ASIC test , DFT, and debug + 2 + years of practical experience with test ... a smarter, connected future for all. As a DFT Engineer you will work with chip architects, chip designers,...work with chip architects, chip designers, implementation engineers and test engineers to verify the DFT and DFD (Design… more
- Meta (Sunnyvale, CA)
- …to Job" online on this web page. **Required Skills:** Product Validation Engineer Responsibilities: 1. The Product Validation Engineer focuses on end-to-end ... introduction, new technology introduction, factory readiness, product launch and post-launch testing. 2 . As such this role will require working closely with a wide… more
- City of Long Beach (Long Beach, CA)
- …at ###. If special accommodation is desired, please contact the Human Resources Department two ( 2 ) business days prior to the test at ###. For the hearing ... BUILDING MAINTENANCE ENGINEER Print (https://www.governmentjobs.com/careers/longbeach/jobs/newprint/4976202) Apply BUILDING MAINTENANCE ENGINEER Salary $31.74… more
- Meta (Sunnyvale, CA)
- …and different subsystems by working with system integration EE team and technology teams 2 . Define and track detailed test plans for the different modules and ... **Summary:** Electrical Design Validation Engineer in Wearables Hardware will be an integral...substantial aspect of design verification & validation, and design test protocols with line-of-sight to mass production. Our team… more
- SpaceX (Hawthorne, CA)
- …work not considered COMPENSATION AND BENEFITS: Pay range: Automation & Controls Engineer / Level I: $100,000.00 - $120,000.00/year Automation & Controls ... design and development of complex in-house automated manufacturing and test systems from concept to production, specifically owning electrical...Engineer / Level II: $115,000.00 - $135,000.00/year Your actual … more
- Meta (Menlo Park, CA)
- …verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification 2 . Develop functional tests based on verification ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Meta (Sunnyvale, CA)
- …IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2 . Develop functional tests based on verification ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Meta (Sunnyvale, CA)
- …IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification 2 . Develop functional tests based on verification ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...verification closure of a design module or sub-system from test -planning, UVM based test bench development to… more
- Rubrik (Palo Alto, CA)
- …execute automated test scripts. Will investigate, triage, and debug hardware/system level issues down to component - hard drive, Network, Platform components and ... we want to talk to you! **About The Role:** The Senior Hardware Engineer will implement hardware development programs from inception to product shipment. Will work… more
- Northrop Grumman (Los Angeles, CA)
- …history, they're making history. **Northrop Grumman Defense System's** is seeking a **Software Quality Engineer level 3 or 4** to join our team of qualified, ... the Advanced Weapons, **SiAW program** . The Software Quality Engineer performs tasks that contribute to the completion of...work as part of a team, demonstrate a high level of attention to detail, possess the ability to… more