- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Custom Timing Engineer to join our dynamic and growing Circuit Solutions Group! If you are looking for a challenging ... and exciting role in improving the netlist and timing quality of our designs and if you are...and reliability of Nvidia's next generation products. + Develop timing models and methodology for custom macro design at… more
- NVIDIA (Santa Clara, CA)
- …and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem ... you'll be doing: + You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... work, to amplify human inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs and SoCs at block… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... I/O interface modeling to architect and deploy robust timing signoff practices across high-performance SoCs. You will play...You will play a critical role in defining cross-domain timing constraints, validating IO timing integrity, and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, ... GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...+ You will be responsible for all aspects of timing including setting up timing constraints, … more
- Cisco (San Jose, CA)
- ASIC Design Technical Leader - Design & Timing Constraints Focus Apply (https://jobs.cisco.com/jobs/Login?projectId=1432242) + Location:San Jose, California, US + ... from concept to first customer shipments **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- SanDisk (Milpitas, CA)
- …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced Cadence...RESPONSIBILITIES: + **Synthesis and DFT scan insertion** + Familiar timing constraint and qualify, clean up timing … more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to highly integrated ... data center connectivity products. Responsibilities Include: + Develop and validate timing constraints for intricate SoC designs. + Perform static timing … more