• Senior SRAM Engineer , Circuit Design

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior SRAM Engineer ! The Full Custom Macro team at NVIDIA designs specialized RAM implementations for NVIDIAs wide array of processing ... + Background with developing and using various flows and methodologies including: Static Timing analysis, EM and IR analysis, Formal Verification At NVIDIA, we have… more
    NVIDIA (10/03/25)
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  • Data Center Capacity Planning Engineer

    NVIDIA (Santa Clara, CA)
    …healthcare. At the heart of our data centers is the ability to engineer coordinated system designs in close coupling to NVIDIA's industry-leading GPU products. We ... highlighting constraints, risks, and available capacity. + Evaluate tradeoffs across timing , location, and develop options to optimize portfolio planning. + Partner… more
    NVIDIA (09/30/25)
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  • ASIC Engineer

    Kelly Services (Folsom, CA)
    **Job Title:** ASIC Engineer **Location** : Folsom, CA **Duration:** 1+ year with possible extensions **Pay Rate:** $115-$120/HR **Position Overview** + Oversees ... the process flow from high-level design to synthesis, place and route, and timing and power use. + Analyzes equipment to establish operation data, conducts… more
    Kelly Services (09/30/25)
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  • Physical Design Flow and Methodology…

    Google (Sunnyvale, CA)
    Physical Design Flow and Methodology Engineer _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring ... EDA tools and RTL To GDS CAD flows such as place and route, EM/IR, static timing , etc. You will also possess a good command of common scripting languages. The AI and… more
    Google (09/28/25)
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  • FPGA Digital Design Engineer 3/4

    Northrop Grumman (Los Angeles, CA)
    …Northrop Grumman Advanced Weapons has an opening for a FPGA Digital Design Engineer with an active clearance, to join our team of qualified, diverse individuals. ... DSP, MATLAB, and SimuLink . Knowledgeable in FPGA physical constraints and achieving timing closure. . Experience with board or system level debug using test… more
    Northrop Grumman (09/27/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …**Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you will be contributing to SerDes ... issues at the chip and block level.** + **Experience with CDC, static timing analysis methodologies and relevant tools.** + **Exposure to SDF annotated simulations… more
    Broadcom (09/26/25)
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  • Power and Performance Engineer - System…

    NVIDIA (Santa Clara, CA)
    …and intelligence. Choose to join us today. NVIDIA Silicon Solutions Group seeks a hardworking engineer to join a silicon HW team. As a team member, you will develop ... EE, digital/analog design, signal integrity, low power design, memory power management techniques, timing analysis, and architecture. + It is crucial to have a deep… more
    NVIDIA (09/25/25)
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  • HSIO Functional Validation Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. NVIDIA's High-Speed Interconnect (HSIC) team is seeking a versatile engineer to be part of a Silicon Hardware team. You will dive ... EE fundamentals, knowledgeable in computer architecture, high speed interfaces, timing analysis, process variations, statistical error rates and power analysis.… more
    NVIDIA (09/12/25)
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  • Senior Low Power Engineer

    NVIDIA (Santa Clara, CA)
    …amplify human inventiveness and intelligence. NVIDIA Silicon Solutions Group seeks a versatile engineer to join a Silicon HW team. You will interpret product goals, ... fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting +… more
    NVIDIA (09/12/25)
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  • Senior Design for Debug Architect and Methodology…

    NVIDIA (Santa Clara, CA)
    …now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software solutions ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
    NVIDIA (09/10/25)
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