• Post-Silicon Hardware Engineer

    NVIDIA (Santa Clara, CA)
    …and help define the future of computing. We seek an experienced Post-Silicon Hardware Engineer to join our Silicon Solutions Group. In this role, you will validate ... debug. + Strong EE fundamentals: digital design, computer architecture, power/ timing /fault analysis, statistics, and scripting. + Deep understanding of… more
    NVIDIA (09/09/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... It involves working with the Physical Design & STA team for DFT mode timing closure. The role could also involve direct interaction with external customers. It is… more
    Broadcom (09/05/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …before you apply.** **Job Description:** Broadcom is looking for highly qualified DFT engineer . In this role you will be contributing to the highly integrated ... verilog and ATE vectors and cross verification. + Experience with GLS and timing analysis. + Experience with silicon bring-up & debug, memory and scan diagnostics.… more
    Broadcom (09/03/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Circuit Design Engineer ! NVIDIA has been redefining computer graphics, PC gaming, and accelerated computing for more than 25 years. ... + Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required. + Basic understanding and experience working with… more
    NVIDIA (09/03/25)
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  • Senior Circuit Design Engineer - Power…

    NVIDIA (Santa Clara, CA)
    …wave of computing. We are now looking for a motivated Senior Circuit Design Engineer in Power Modeling and Simulation to join our dynamic and growing Circuits ... you are looking for a significant and exciting role in improving the netlist and timing quality of our designs and if you are a strong self-starter and highly… more
    NVIDIA (08/29/25)
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  • Senior ASIC Design Engineer - Circuits

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... of ASIC design flow including front end design and verification, DFT, and timing analysis + Strong team player with outstanding interpersonal skills. Ways to stand… more
    NVIDIA (08/27/25)
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  • Lead Post-Silicon Validation Engineer

    NVIDIA (Santa Clara, CA)
    We are seeking Lead Post-Silicon Validation Engineer within the GPU Engineering Team to help drive development of future GPUs be used in 3D graphics, deep learning, ... in DRAM, high speed DRAM Interfaces like HBM, GDDR and LPDDR and their timing , analog, and digital requirements. + In Pre-Silicon phase, work with the design and… more
    NVIDIA (08/21/25)
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  • Senior Principal Digital Design Engineer

    Leonardo DRS, Inc. (Cypress, CA)
    …surveillance and targeting applications. We are seeking a Senior Principal Digital Design Engineer to join the company in the development of strategic space and ... simulation, synthesis, resource and power utilization analysis, place and route, timing analysis, verification, and integration activities + Block level and chip… more
    Leonardo DRS, Inc. (08/21/25)
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  • Principal Software Engineer - Vehicle…

    General Motors (Mountain View, CA)
    …of the embedded system requirements, Inter ECU communications, and stringent timing requirements._ + _Technical: Java / C++, operating systems and runtime ... and verbal technical communication skills, excellent ability to incorporate other engineer 's ideas and explain their own._ _Compensation_ : The compensation… more
    General Motors (08/15/25)
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  • IC Design Engineer

    Broadcom (Irvine, CA)
    …compute cores and CPUs. We are seeking a motivated and technically strong engineer to join our team. Job Description: Layout design of digital high-performance ... blocks Timing closure of the blocks with best PPA (power/performance/area) Debug LVS/DRC/ERC errors with verification tool Analyze the trade-offs and performance… more
    Broadcom (08/08/25)
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