• Senior Methodology Engineer , CAD Tool…

    NVIDIA (Santa Clara, CA)
    …a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ! In ... experience + 3+ years of experience in VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in multiple… more
    NVIDIA (07/22/25)
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  • ASIC Design Engineer , Cloud-Scale Machine…

    Amazon (Cupertino, CA)
    …area requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and clock ... other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks. You will thrive… more
    Amazon (10/18/25)
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  • DSP or Serdes RTL Sr Principal Digital Design…

    Cadence Design Systems, Inc. (San Jose, CA)
    …of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding ... of fundamental physical design flows and stages + Understanding impacts of analog and mixed-signal design and verification on digital-on-top development flow. + Exhibit excellent communication skills and be self-motivated and well organized. + Experience with… more
    Cadence Design Systems, Inc. (10/17/25)
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  • Applied Machine Learning Engineer , Circuit…

    NVIDIA (Santa Clara, CA)
    …of silicon data, manufacturing process variation analysis, VLSI circuit design and timing etc. + Responsible for translating the requirements into a data science ... (or equivalent experience). + Experience with VLSI, Circuit Design, CMOS Device Physics, Timing , ASIC, EDA is a strict requirement for this role. + Shown ability… more
    NVIDIA (10/10/25)
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  • Senior ASIC Design Engineer , Project…

    Amazon (San Diego, CA)
    …in silicon from system specification to chip specification to RTL to optimizing timing / power to chip level validation . Develop solutions optimizing customer ... constructed using UVM, System C and DPI-C . Ensure that the block meets DFT, timing and power targets by working closely with the implementation team . Learn about… more
    Amazon (10/08/25)
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  • Physical Design Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... Clock tree synthesis methods and techniques + Strong background in STA, extraction, timing and RC correlation + Background with design rules in advanced nodes and… more
    NVIDIA (09/23/25)
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  • Sr. Principal EDA Software Engineer (C++,…

    Cadence Design Systems, Inc. (San Jose, CA)
    …experience in development of EDA tools and one or more of transistor level timing , power, noise, aging, reliability, and emir analysis + Hardcore C++ Knowledge - ... be focused on: + Enhancing and expanding the existing tools' architecture to cover timing analysis + Creating new frameworks for analysis of effects dominant at n5… more
    Cadence Design Systems, Inc. (09/23/25)
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  • Applied Machine Learning Engineer - Circuit…

    NVIDIA (Santa Clara, CA)
    …of silicon data, manufacturing process variation analysis, VLSI circuit design and timing etc. + Responsible for translating the requirements into a data science ... in Electrical/Computer Engineering + Experience with VLSI, Circuit Design, CMOS Device Physics, Timing , ASIC, EDA is a strict requirement for this role + Experience… more
    NVIDIA (08/29/25)
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  • Staff Logic Circuit Design Engineer

    Micron Technology, Inc. (Folsom, CA)
    …knowledge of digital design and RTL development + Good understanding on timing /area/power/complexity tradeoffs in designs + Experience with Synthesis & Constraints + ... You Apart:** + Experience with UPF, power analysis, DFT/scan insertion, ATPG, generating timing models + Experience with scripting in languages like Python, Perl +… more
    Micron Technology, Inc. (08/22/25)
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  • Senior Physical Design Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... Clock tree synthesis methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design rules in advanced nodes… more
    NVIDIA (08/20/25)
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