• ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... techniques and generate optimized gate level netlist for Timing , Area, and Power. 2. Debug timing /area/congestion...for Timing , Area, and Power. 2. Debug timing /area/congestion issues and resolve w/ RTL & physical designers.… more
    Meta (09/20/25)
    - Related Jobs

  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …make an impact on the world of technology. Responsibilities; Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and ... delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies....Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing , Distributed and Concurrent STA flows. . Work efficiently… more
    Cadence Design Systems, Inc. (08/14/25)
    - Related Jobs

  • Senior ASIC Physical Design Engineer…

    NVIDIA (Santa Clara, CA)
    …and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to challenge ... checks, etc. + Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and… more
    NVIDIA (10/07/25)
    - Related Jobs

  • Physical Design Engineer (Silicon…

    SpaceX (Sunnyvale, CA)
    Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... with the ultimate goal of enabling human life on Mars. PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
    SpaceX (10/07/25)
    - Related Jobs

  • Principal Engineer , VLSI Design…

    SanDisk (Milpitas, CA)
    …you'll be at the center of innovation. We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory Design team. This is a great ... memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area… more
    SanDisk (09/11/25)
    - Related Jobs

  • Staff Engineer , VLSI Design…

    SanDisk (Milpitas, CA)
    …you'll be at the center of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a great ... memory, focusing on micro architecture, RTL design, verification, logic synthesis, and timing analysis to deliver a design meeting target power, performance and area… more
    SanDisk (09/10/25)
    - Related Jobs

  • R GPS Navigation / Principal GPS Navigation…

    Northrop Grumman (Los Angeles, CA)
    …of our mission! We are looking for you to join our team as a Systems Engineer focused on GPS Navigation based out of Woodland Hills, CA. As a Systems Engineer ... Mission Systems sector is seeking a GPS Navigation Systems Engineer to join our diverse and talented team in...ONR, and Army labs to develop advanced navigation and timing technologies. + Work with a team of navigation… more
    Northrop Grumman (08/31/25)
    - Related Jobs

  • Consulting Engineer - Navigation Systems…

    Northrop Grumman (Los Angeles, CA)
    …looking for a **Navigation Architect** to support the Future Positioning, Navigation, and Timing (FPNT) organization in **Woodland Hills, CA** . Our team is focused ... systems, GPS-Denied navigation, multi-sensor fusion, quantum sensing, clocks and timing systems, distributed and cooperative sensing, and emerging space-based… more
    Northrop Grumman (09/23/25)
    - Related Jobs

  • Senior Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …IO's and macros. + Work on power grid planning, Clock tree Synthesis (CTS) and timing closure. + Multi mode and multi corner timing closure, RC extraction, Cross ... analysis. + Work with the Front-end teams to update and tune timing constraints. + Debugging timing violations and rolling in functional, Timing ECO's and… more
    NVIDIA (07/24/25)
    - Related Jobs

  • Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies...emphasis on Cadence tools of Synthesis, Physical Design & timing closure at 20nm or below nodes + Prior… more
    Cadence Design Systems, Inc. (09/09/25)
    - Related Jobs