- SanDisk (Milpitas, CA)
- …circuit simulations to meet all performance specifications. + RTL design, synthesis, static timing analysis and verification in verilog for page buffer and data path ... control logics. + Conduct silicon debugging and evaluation with micro-probing. + Collaborate with characterization engineers to fully characterize silicon, and partner with other designers to develop solutions for silicon issues. + Generate detailed technical… more
- NVIDIA (Santa Clara, CA)
- …required. + Experience in Spice simulation and analysis. + Understanding of timing closure, interconnect design, and custom circuits are required. + Understanding of ... Place and Route design tools and datapath Tiling techniques is required. + Hands on experience in design and analysis of low power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design-for-test (DFT) and logic design is a plus. +… more
- Broadcom (San Jose, CA)
- …design trade-offs to drive attainment on metrics such as power, jitter and timing budget. + Experience in assessing design bugs and recommending fixes or workarounds ... to balance technical requirements with schedule. + Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals. + Good understanding of signal integrity… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …is a must. + Must be familiar with digital Place and Route methodology, static timing analysis and at least one scripting language such as perl or TCL. + Must ... have excellent debugging skills and an ability to separate out the critical issues from trivial ones. + Must possess superior communication skills, an outgoing personality and an ability to build a rapport with the customer + Be proud and passionate about the… more
- Vector Atomic (Pleasanton, CA)
- …practical quantum devices for applications like GPS-free navigation and timing , geophysical exploration, and telecommunications. We are committed to delivering ... near-term solutions that leverage the unique capabilities of quantum systems, engineered for real-world integration. We are seeking talented Opto-mechanical Engineers to join our growing team of 70+ innovators. In this hands-on role, you will be instrumental… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... understanding of firmware/driver structures and their interaction with hardware. + Solid understanding of PVT dependencies and binning methodologies. + Knowledgeable in performance and power management techniques such as DVFS, clock and power gating, clock… more
- Cardinal Health (Sacramento, CA)
- …willingness to buy Cardinal Health's solution (Why Cardinal Health?), the timing (Why Now?), or the customer's satisfaction, and contract negotiations. The ... Senior Consultant, Technical Sales role is responsible for closely collaborating across functions within OptiFreight(R) Logistics to create and maintain a pipeline of customers for advanced logistics management technology products and program experience. The… more
- Ford Motor Company (Palo Alto, CA)
- …pipelines. * Define and maintain interface specifications (signals, diagnostics, timing budgets, communication protocols) across domains. * Partner with calibration ... and attribute teams to ensure vehicle-level attributes (driveability, responsiveness, safety, NVH) are met. * Provide technical mentorship to junior integration engineers and operators. * Support vehicle testing at proving grounds, winter test sites, and… more
- Amazon (Cupertino, CA)
- …of physical design: full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity analysis, and physical ... verification * Write Tcl or PERL scripts to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications Bachelors' degree or higher in Electrical Engineering, Computer… more
- quadric.io, Inc (Burlingame, CA)
- …+ Own Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + ... BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design + Proficiency in SystemC, SystemVerilog, or Verilog + Strong background in computer architecture + Knowledge of design techniques for low power… more