- Amazon (Cupertino, CA)
- …of physical design: full chip floorplanning, circuit analysis, power/clock distribution, timing optimization, place and route, power integrity analysis, and physical ... verification * Write Tcl or PERL scripts to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications Bachelors' degree or higher in Electrical Engineering, Computer… more
- quadric.io, Inc (Burlingame, CA)
- …+ Own Power, Performance & Area (PPA) optimization + Contribute to timing closure through full product cycle (front end, back-end, tapeout) Requirements: + ... BS/MS or Ph.D. in Electrical or Computer Engineering with a minimum of five years of CPU/GPU/ASIC front-end design + Proficiency in SystemC, SystemVerilog, or Verilog + Strong background in computer architecture + Knowledge of design techniques for low power… more
- NVIDIA (Santa Clara, CA)
- …fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting + Hands-on ... validation lab experience with silicon bringup, lab debug and lab tools (oscilloscopes, multimeters, logic analyzers). + Experience with ASIC power saving features and methods + Deep understanding of firmware/driver structures and their interaction with HW. +… more
- Broadcom (San Jose, CA)
- …cost over the project lifetime.** + **Experience in synthesis, CDC, static timing analysis.** + **Exposure to SDF annotated simulations with good understanding of ... parasitic delays.** + **Experience in design management with detailed knowledge of development methodologies, design flows including EDA integration, foundry PDK and associated collaterals.** + **Strong analytical thinking and problem-solving skills with… more
- Amazon (Cupertino, CA)
- …designers, testing, and transition to manufacturing. Applying skills in simulation, timing analysis, thermal analysis, and EMC is expected. AWS Infrastructure ... Services owns the design, planning, delivery, and operation of all AWS global infrastructure. In other words, we're the people who keep the cloud running. We support all AWS data centers and all of the servers, storage, networking, power, and cooling equipment… more
- NVIDIA (Santa Clara, CA)
- …a plus. + Knowledge of PCB design and consideration for layout, routing, and timing constraints, DFM, DFA, and DFT constraints in volume manufacturing is helpful. + ... You should have an understanding of High-Density Interconnect PCB layout and PCB Signal Integrity. + Proven ability to work with a team while taking personal responsibility for your own contributions + Agility in changing focus as the needs of our effort… more
- SanDisk (Milpitas, CA)
- …architectures and other clock recovery and schemes. + In-depth knowledge of Timing budgeting and Analysis in custom high-speed designs + Working knowledge of ... SI/PI Analysis with various models like IBIS/SPF etc + Very analytical in nature and able to work in a multi-disciplinary environment + Creative, out-of-the-box thinker with a high level of personal involvement + Strong theoretical background with a pragmatic… more
- Ford Motor Company (Long Beach, CA)
- …between application software and firmware. . Develop multicore, timing -critical software architectures. . Work with/resolve ambiguity in ... requirements/specifications/designs. . Create elegant, efficient real-time software components and interfaces. . Develop software component testing methodologies and implementations to ensure maturity/stability/release readiness. . Work with hardware and… more
- Amazon (Sunnyvale, CA)
- …powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of ... Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex,… more
- Amazon (Sunnyvale, CA)
- …powering the latest generation of Echo devices is looking for a Senior SoC Design-STA Engineer to continue to innovate on behalf of our customers. We are a part of ... Crosstalk Delay and Crosstalk Noise analysis for digital ASIC/SoCs. * Full chip timing constraints development, full chip / Sub-System STA and Signoff for a complex,… more