• Sr. ASIC Modem Design Engineer , Project…

    Amazon (Sunnyvale, CA)
    …around the world. Come work at Amazon! We're hiring a Sr. Modem Design Engineer within a high performance ASIC design team. This team is using industry leading ... system specification to chip specification to RTL to optimizing timing / power to chip level validation. . Develop...and/or DPI-C. . Ensure that the block meets DFT, timing and power targets by working closely with the… more
    Amazon (10/11/25)
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  • Senior Signal and Power Integrity Engineer…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board...of circuit design, board/pkg technology & design, link architecture, timing budget methodologies. Your base salary will be determined… more
    NVIDIA (10/10/25)
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  • Senior Signal and Power Integrity Engineer…

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... PCBs and spice-based time domain simulations. + Background with a system level timing or loss budget including silicon, package and board impairments. + Familiarity… more
    NVIDIA (10/09/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for noise… more
    NVIDIA (10/04/25)
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  • ASIC Engineer , IP Design, Silicon

    Google (Mountain View, CA)
    ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL quality checks (eg,… more
    Google (10/03/25)
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  • Senior NAVWAR Engineer

    SAIC (El Segundo, CA)
    …an experienced engineer to join the Positioning, Navigation, and Timing (PNT) Enterprise Systems Engineering & Integration (SE&I) Navigation Warfare (NAVWAR) ... Positioning System (GPS) remains the gold standard for positioning, navigation, and timing . A successful candidate will collaborate and communicate with the SE&I… more
    SAIC (10/02/25)
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  • Senior CPU Physical Design Engineer…

    Google (Mountain View, CA)
    Senior CPU Physical Design Engineer , Silicon _corporate_fare_ Google _place_ Austin, TX, USA; Mountain View, CA, USA **Mid** Experience driving progress, solving ... metrics, and analyzing data trends. + Knowledge of Static Timing Analysis including sign-off corner definitions. + Knowledge of...+ Work on sign off areas such as Static Timing Analysis and Electrical Checks. Information collected and processed… more
    Google (10/01/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into the overall SOC design… more
    NVIDIA (09/30/25)
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  • FPGA Engineer , Platforms, Hardware

    Google (Sunnyvale, CA)
    FPGA Engineer , Platforms, Hardware _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more ... SystemVerilog. + Experience in the FPGA/ASIC development lifecycle, including synthesis, timing closure, and logic simulation. + Experience with common hardware… more
    Google (09/28/25)
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  • HSIO Electrical Validation Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. NVIDIA's High-Speed Interconnect (HSIC) team is seeking a versatile engineer to be part of a Silicon Hardware team. You will dive ... compliance. + Execute validation of signal integrity (SI), power integrity (PI), timing margins, equalization tuning, and error metrics across PCIe Gen5/Gen6, C2C,… more
    NVIDIA (09/24/25)
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