• ASIC Design Engineer

    Broadcom (San Jose, CA)
    …static timing analysis. You will either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years of ... , verification, and synthesis. Must have strong UNIX-based EDA tool skills and knowledge of ASIC design flows. Must be familiar with reusable HDL coding styles… more
    Broadcom (04/26/25)
    - Related Jobs

  • Senior Thermal Design Engineer

    NVIDIA (Santa Clara, CA)
    We are looking for a highly motivated Senior Thermal Product Design Engineer to join this dynamic and innovative team to support the next generation of products ... One Team model , you will support collaborative product design and development activities focusing on one business and...+ Strong proficiency in at least one thermal simulation tool (eg, Icepak, Flotherm, Fluent) + Hands-on experience and… more
    NVIDIA (06/13/25)
    - Related Jobs

  • Principal Engineer , VLSI Design…

    SanDisk (Milpitas, CA)
    …where you'll be at the center of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory Design team. This is a ... revenue opportunities for the company. Join the Memory Technology Design Team and become a leader of this highly...10 years of relevant experience + Experience with chip level integration, chip lead, and full product life cycle… more
    SanDisk (07/17/25)
    - Related Jobs

  • Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …for Block level Physical Implementation. Experience in low power physical design with ICC2/FC tool set, good debugging and scripting (TCL/PERL) skills ... The candidate will be responsible to complete critical block level physical design implementation from netlist to...Requirements: - 2+ yrs. of working experience in physical design with ICC2/FC tool set from netlist… more
    Qualcomm (05/03/25)
    - Related Jobs

  • Digital Design Application Engineer…

    Cadence Design Systems, Inc. (San Jose, CA)
    …on the world of technology. As an expert Digital Implementation Field Applications Engineer (AE) , you will work side-by-side with our leading edge customers. With ... and Signoff to meet/exceed their PPA targets, achieve faster design closure, and turn their design concepts...tools and technologies + Efficiently translate customer requirements into tool solutions by working closely with R&D Job Requirements… more
    Cadence Design Systems, Inc. (06/02/25)
    - Related Jobs

  • CPU Physical Design Pathfinding…

    Qualcomm (San Diego, CA)
    …Pathfinding Engineer , you will work with Architecture, RTL, Physical Design , Circuits, CAD and Post-Silicon teams to lead the cutting-edge technology development ... Strong data analytical skills to identify and address physical design issues. + Experience in pre-post silicon correlation Roles...propose impactful PPA optimizations. + Engage with external CAD tool vendors and internal CAD teams to identify and… more
    Qualcomm (07/03/25)
    - Related Jobs

  • Senior Digital Design Engineer

    Umbra Lab (Santa Barbara, CA)
    …meaningfully existed before. Join our dynamic Space Systems team as a Senior Digital Design Engineer , where you'll be at the forefront of creating cutting-edge ... to the highest quality commercial satellite data available, which is an indispensable tool for the growing number of organizations monitoring the Earth. We empower… more
    Umbra Lab (07/01/25)
    - Related Jobs

  • Principal / Sr Principal Design…

    Northrop Grumman (Manhattan Beach, CA)
    …making history. Northrop Grumman Defense Systems is seeking a **Principal / Sr Principal Design Engineer :** **CPLM SME - Gen** **eral** . This position is ... be filled at either a Principal or Sr. Principal Engineer level . **What You'll Get to Do:**...and common user issues for training opportunities + Perform tool testing. + Assist with creating and maintaining product… more
    Northrop Grumman (05/30/25)
    - Related Jobs

  • GPU Physical Design Engineer…

    Qualcomm (San Diego, CA)
    …collaboration with verification, timing, power, and packaging teams to ensure holistic design convergence + Partnering with EDA tool vendors and internal ... IP experience which includes bus/pin/repeater planning at the top level + Strong background in VLSI design ,...top level + Strong background in VLSI design , physical implementation and scripting + Strong background and… more
    Qualcomm (05/28/25)
    - Related Jobs

  • GPU- Physical Design Engineer

    Qualcomm (San Diego, CA)
    …netlist to GDS of very complex and high frequency blocks or top level . This includes floor-planning, placement, clock implementation and routing of very high gate ... count design to meet very aggressive Power, Performance and Area...to be involved in collaboration with multi-disciplined teams and tool vendors to develop/enhance automation in flows and methodologies… more
    Qualcomm (07/02/25)
    - Related Jobs