• Senior Signal and Power Integrity Engineer

    NVIDIA (Santa Clara, CA)
    …crafting creative Signal and Power Integrity solutions to complex system design problems. + System-level power integrity simulations of high-performance AI systems, ... + Work closely with VLSI power teams and package/board design teams to design , optimize, and model...power or I/O power. + Strong understanding of how die /package/board decoupling impacts power supply noise across different frequency… more
    NVIDIA (12/22/25)
    - Related Jobs
  • Wafer Backside Processing Technician

    Teledyne (Goleta, CA)
    …factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration ... supports production and engineering priorities in a cleanroom environment, focusing on die preparation, hybridization, wicking, and wire bonding processes. This is a… more
    Teledyne (10/09/25)
    - Related Jobs
  • Senior Mechanical Engineer

    Cisco (San Jose, CA)
    …or related degree with 7+ years of relevant experience *Experience with Aluminum Die -cast and sheet metal design *Prior experience with CAD tools such ... the most extreme environmental conditions in the industry. We design our hardware to meet specific temperature, shock and...and IP67) *Experience with tooling vendor management (DFM, Hard tool bring up, FAI) *Experience with ISO standards for… more
    Cisco (12/13/25)
    - Related Jobs
  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an ... and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and...drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the… more
    NVIDIA (11/20/25)
    - Related Jobs
  • Signoff Methodology Engineer - New College Grad

    NVIDIA (Santa Clara, CA)
    …of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 5 nm and beyond, this is an ... and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and...drop etc. + Collaborate with technology leads, VLSI physical design , and timing engineers to define and deploy the… more
    NVIDIA (11/05/25)
    - Related Jobs
  • Quality Manager

    Fujifilm (Santa Clara, CA)
    …their printheads. We are a recognized leader in the manufacturing and design of durable and productive drop-on-demand inkjet printheads that power cutting-edge ... available production capacity. + Works with Engineering, QA and design teams to define quality plans for the products....plans for the products. Drives the documentation of critical product/process/ tool parameters & how to monitor them for early… more
    Fujifilm (12/16/25)
    - Related Jobs
  • Chip Power Integrity Engineer

    Broadcom (San Jose, CA)
    …integrity problems for a variety of products including 2.5D, spanning from small die with high impedance challenges to massively large chips with large power ... using HSPICE or ADS + In-depth knowledge of Redhawk-SC tool is preferred + Know-how in Totem flow and...is nice to have + Familiarity with entire VLSI design flow and tools (Cadence/Synopsys/Mentor) and scripting languages (Tcl,… more
    Broadcom (11/06/25)
    - Related Jobs