- Siemens (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital , mixed-signal, and analog IC chip designs based ... planning, Testbench development using SV/ UVM methodologies, Functional verification and modeling of digital /mixed-signal ASICs and SoCs, Failure… more
- Meta (Sunnyvale, CA)
- …at the entire stack, through algorithms to architecture, transistors to firmware.As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
- Siemens (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital , mixed-signal, and analog IC chip designs based ... planning, Testbench development using SV/ UVM methodologies, Functional verification and modeling of digital /mixed-signal ASICs and SoCs, Failure… more
- BAE Systems (San Diego, CA)
- …be available based on position level and/or job specifics. **Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)** **113449BR** EEO Career ... your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification environments.… more
- Google (Mountain View, CA)
- …with verifying digital logic at RTL using SystemVerilog or Universal Verification Methodology ( UVM ). Preferred qualifications: + Master's degree or PhD in ... Learn more about benefits at Google (https://careers.google.com/benefits/) . + Plan the verification of digital design blocks by fully understanding the design… more
- Amazon (San Diego, CA)
- …or Ph.D degree in Electrical / Communications Engineering - 2+ years in digital verification , preferably in communication systems - Familiarity with Matlab - ... Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM , SystemC and DPI-C .… more
- Amazon (San Diego, CA)
- …Master's or Ph.D degree in Electrical / Communications Engineering * 10+ years in digital verification * Hands on experience working closely with Systems team on ... * Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM , System C and DPI-C *… more
- Qualcomm (San Diego, CA)
- …that meet performance, security, technology, and feature requirements. As a Design Verification Engineer , you will work with Chip Architects to validate ... to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer , you will plan, design, optimize, verify, and test… more
- SpaceX (Sunnyvale, CA)
- Principal ASIC Verification Engineer Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... goal of enabling human life on Mars. PRINCIPAL ASIC VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're... and test bench development + 10+ years of UVM , OVM, or VMM experience PREFERRED SKILLS AND EXPERIENCE:… more
- The Boeing Company (Mountain View, CA)
- …Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us as part of our ... enable high-integrity, low SWAP-C flight computers. And we're applying the latest digital IC design processes with industry-best tools to enable applications that… more
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