• ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    …with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also… more
    Meta (10/30/25)
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  • Senior Verification Engineer - Hardware

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Verification Engineer to join our Emulation division. We are a worldwide recognized division noted for groundbreaking technology. We are ... Join us today! What you will be doing: + We support multiple emulation environments using the latest emulation techniques (C/C++ DPI Transactors, SV… more
    NVIDIA (10/28/25)
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  • ASIC Engineer , Performance & Package…

    Meta (Sunnyvale, CA)
    …with the Design team 5. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking...simulation, you will use other approaches like Formal and Emulation to achieve a bug-free design. The role also… more
    Meta (11/19/25)
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  • ASIC Engineer , Design Verification

    Meta (Sunnyvale, CA)
    …Design team. 8. They will collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design ... "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Leverage Design Verification experience to build… more
    Meta (11/01/25)
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  • Lead Embedded Software Engineer

    Capgemini (Santa Clara, CA)
    …the job you're considering** We are seeking a highly seasoned Lead/Manager Embedded Software Engineer to join our dynamic team. In this role, we will lead and ... ARM CPUs and DSPs. You will work in pre-silicon (virtual, emulation , and FPGA platforms) and post-silicon (bring-up boards, non-form-factor) environments. Your… more
    Capgemini (10/10/25)
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  • Sr Principal Product Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …impact on the world of technology. Job Title: Senior Principal Product Engineer Location: Global (remote) Reports to: Technical Business Development Director Job ... Overview: The Senior Field Applications Engineer (FAE) position serves as a key technical liaison, transforming VLAB's advanced virtual hardware solutions into… more
    Cadence Design Systems, Inc. (11/08/25)
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  • Custom SOC IP Verification Engineer

    NVIDIA (Santa Clara, CA)
    …interconnect fabric. + Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation , and Post-Silicon Validation teams to ensure comprehensive ... NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and...+ Exposure to coherency modeling tools, verification IPs, or emulation platforms (eg, Palladium, Veloce). + Experience in GPU-based… more
    NVIDIA (09/20/25)
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  • Design Verification Engineer

    Meta (Sunnyvale, CA)
    …and code coverage 4. Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design ... through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement verification plans, and… more
    Meta (11/08/25)
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  • Senior Design Verification Engineer , HW…

    Amazon (Sunnyvale, CA)
    …powering the latest generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate on behalf of our customers. We are a part ... will participate in the lab bring-up of these blocks either in FPGA, emulation , or silicon by potentially writing test scripts, analyzing lab data, proposing… more
    Amazon (09/04/25)
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  • IC Design Engineer

    Broadcom (Irvine, CA)
    …power checks using UPF/CPF flows and ECO implementation. + Support system level validation efforts on FPGA/ emulation + Support silicon bring-up and debug efforts ... before you apply.** **Job Description:** **Job Description: IC Design Engineer ** + Participate in IP level architectural definition including micro-architecture… more
    Broadcom (11/18/25)
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