- Amazon (Cupertino, CA)
- …solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our ... will help each team member develop into a better-rounded engineer and enable them to take on more complex...or other related discipline - 3+ years of design verification experience using System Verilog and UVM - 3+… more
- Broadcom (San Jose, CA)
- …Architect and develop scalable and re-usable testbenches, using the framework of the verification methodology + Build pseudo-random tests to verify and get to full ... Coverage gaps and improve tests to cover the gaps + Document verification strategy including Test plans, Verification Environment, pseudo-random tests, etc.… more
- Amazon (San Diego, CA)
- …technologies. In this role you will: . Implement a state of the art verification environment for modem IP and subsystem to facilitate testing of the DUT against ... with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C . Develop a… more
- quadric.io, Inc (Burlingame, CA)
- …processors + Collaborate with architects, HW & SW designers to document verification test plans + Implement testbenches using commercial VIPs and/or internal SW ... Use coverage metrics to track and communicate progress on verification Requirements + At least 5 years of experience...+ At least 5 years of experience in design verification for CPU or GPUs. + Deep knowledge of… more
- Amazon (Cupertino, CA)
- …in 190 countries around the world. We are seeking an experienced Design Verification Engineers to build the next generation of our cloud server platforms. Our ... solutions achieve their desired functionality, developing and executing multi-faceted verification /validation plans, and measuring the teams progress towards our… more
- Teradyne (Agoura Hills, CA)
- …quality leadership in the Automated Test Equipment (ATE) industry. The Software Quality Engineer is an integral member of the QE team, using and developing automated ... Quality Engineering team is looking for a highly motivated, energetic, software engineer who will work collaboratively with the test and development teams as… more
- Amazon (Cupertino, CA)
- …high performance at low cost. Key job responsibilities - Develop formal verification plans, implement and verify state-of-the-art IP architectures. - Work with block ... engineering, or related field - 7+ years of practical experience with formal verification as IP/Block owner, or equivalent academic experience in formal methods. -… more
- Amazon (Cupertino, CA)
- …and Japan, and customers across all industries. We are seeking experienced Design Verification Engineers to build the next generation of our cloud server chips. Our ... or CS or CE. - 8+ years of design verification experience using System Verilog and UVM - 8+...and fullchip SOC system testing. - Experience using multiple verification platforms. - Experience with C/C++ and Object-Oriented Programming.… more
- Cisco (San Francisco, CA)
- …contribute to system and processor architecture, high-speed logic design and verification , digital signal processing, memory and custom library development, physical ... timing closure. **Preferred Qualifications** ** ** + Experience with ASIC verification methodologies (eg, UVM, SystemVerilog) + Understanding of physical design and… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …who want to make an impact on the world of technology. Principal Software Engineer - Low-Power Verification (Palladium & Protium) We are seeking a highly ... skilled Senior Software Engineer to help build the next generation of low-power verification software for the Palladium and Protium emulation platforms. In this… more