- L3Harris (Camden, NJ)
- …land, sea and cyber domains in the interest of national security. Job Title: ASIC /FPGA Design Engineer (SMES) Job Code: 32295 Job Location: Camden, NJ Schedule: 9/80 ... 15,000 . Job Description: Reporting to the Manager, Engineering ( ASIC /FPGA), the Senior Member of Engineering Staff (SMES) will...Engineering Staff (SMES) will be part of the key ASIC /FPGA design team, responsible for the delivery of FPGA/ASICs… more
- Lockheed Martin (Denver, CO)
- **Description:** Join Our Team as an ** ASIC /FPGA Principal SoC Engineer** where you will work on the development of a sophisticated state\-of\-the\-art avionics ... development for the department, this role: * Supports all aspects of ASIC , FPGA, SoC development, to include architecture, design, and analysis, seeking opportunity… more
- RTX Corporation (El Segundo, CA)
- …the Microelectronics Technology team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, ... tools and practices for continuous improvement in the group's ASIC / FPGA design flow + Contribute to engineering...blocks using VHDL or System Verilog + Proficiency using ASIC and/or FPGA simulation and synthesis tools (eg Modelsim,… more
- Cisco (San Francisco, CA)
- …opens. Applications are accepted until further notice. **Meet the Team** The ASIC Group works closely with other development teams within Cisco, including marketing, ... billions globally. **Your Impact** ** ** Join our award-winning ASIC team, where you'll collaborate with top industry talent...(eg, Python, Perl, TCL) for automation. + Familiarity with ASIC /SoC design flow including synthesis, place & route, and… more
- Palo Alto Networks (Santa Clara, CA)
- …drives great outcomes. **Your Career** As a Design Verification engineer on the ASIC team, you will ensure that the ASICs in our groundbreaking next-generation ... in close collaboration with system architects, software engineers, and ASIC designers + Define new tools and methodologies to...- MSEE preferred + Minimum 5 years experience in ASIC design verification + Demonstrated success in taking multiple… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking elite ASIC Verification Engineers to verify the design and implementation of the world's leading SoC's and GPU's. This position offers the ... be doing: + As a key member of our ASIC Verification team, you will verify the design and...+ You will be responsible for verification of the ASIC design, architecture, golden models and micro-architecture using advanced… more
- Northrop Grumman (Roy, UT)
- …Defense Systems is seeking a **Manager of Programs 2 - Honeywell (HI) ASIC (Application Specific Integrated Circuit) SMTL (Supplier Management Team Lead)** . This ... **What you will get to do:** As the Honeywell ASIC SMTL, you will lead a dynamic cross functional...Years of Experience working with ASICs or on an ASIC Program. + Familiarity with DoD ASIC … more
- Ralliant (Boulder, CO)
- …Overview** Tektronix is seeking a highly skilled and innovative Principal Analog/Mixed-Signal ASIC Designer to join our dynamic team in either Louisville, Colorado, ... signal integrity and system-level analysis for interfaces external to the ASIC . + Create and execute comprehensive characterization plans; analyze and interpret… more
- Northrop Grumman (Linthicum Heights, MD)
- …and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts + Responsible with ... ASIC development process. + Knowledgeable in VHDL, Verilog or...hired + Experience in full product life cycle of ASIC Design + Experience with Cadence and/or Mentor test… more
- Teledyne (Goleta, CA)
- …of being on a team that wins. **Job Description** **Job Summary:** ASIC Digital Design Engineer: Oversees definition, design, verification, and documentation for ... ASIC development. Determines architecture design, logic design, and system...windowing). + Finite State Machine and datapath design for ASIC modes. + Clock domain crossing and power-aware RTL… more