• Senior Design For Test Engineer

    Microsoft Corporation (Santa Clara, CA)
    …to CPU-based alternatives Microsoft DPU team in Santa Clara is looking for a Senior Design For Test Engineer to help develop their next generation complex SoCs ... manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and...experience. + 2+ years of industry experience as a Design For Test (DFT) engineer . + Hands… more
    Microsoft Corporation (07/31/25)
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  • Principal Engineer - Silicon One Software

    Cisco (Boxborough, MA)
    …are received. **Meet the Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934) +...design teams to define the next generation of ASIC products being developed. You will work multi-functionally with… more
    Cisco (08/02/25)
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  • Principal Design Engineer

    Microsoft Corporation (Raleigh, NC)
    …engineers to help achieve that mission. We are looking for a **Principal Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... globalization, and manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and partners worldwide… more
    Microsoft Corporation (07/25/25)
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  • Hardware Design Engineer 4

    ManpowerGroup (Mountain View, CA)
    Our client, a leader in technology innovation, is seeking a Hardware Design Engineer 4 to join their team. As a Hardware Design Engineer 4, you will be ... abilities which will align successfully in the organization. **Job Title: Hardware Design Engineer 4** **Location: Mountain View, CA - Onsite** **Pay… more
    ManpowerGroup (08/09/25)
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  • Network Production Engineer , Design

    Meta (Menlo Park, CA)
    …maximum reliability, scalability, and efficiency . **Required Skills:** Network Production Engineer , Design Responsibilities: 1. Design network topologies ... at Meta are hybrid software and network engineers who design , build, and operate our worldwide Data Center network....Understanding of different Optics and internals of a switch ASIC 20. Familiarity with the Linux based systems **Public… more
    Meta (08/01/25)
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  • Senior Design Verification Engineer

    Microsoft Corporation (Redmond, WA)
    …manage and optimize the Cloud infrastructure. We are looking for a **Senior Design Verification Engineer ** to join the team. **Responsibilities** + Establish ... manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and...yourself as an integral member of a design verification team for the development of AI components… more
    Microsoft Corporation (08/08/25)
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  • CPU Server Physical Design Timing…

    Qualcomm (Santa Clara, CA)
    …develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design ... create designs that push the envelope on performance, energy efficiency and scalability. **About The Role:** In this role...Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and… more
    Qualcomm (07/23/25)
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  • Senior Design Engineer

    Microsoft Corporation (Redmond, WA)
    …engineers to help achieve that mission. We are looking for a **Senior** ** Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System ... globalization, and manageability solutions. Our focus is on smart growth, high efficiency , and delivering a trusted experience to customers and partners worldwide… more
    Microsoft Corporation (08/08/25)
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  • Staff Hardware Systems Design…

    Google (Sunnyvale, CA)
    …or equivalent practical experience. + 6 years of experience working in a hardware systems design , or 5 years of experience with an advanced degree. + 3 years of ... experience in technical leadership. + Experience with power circuit design and signal integrity. **Preferred qualifications:** + PhD in Electrical Engineering,… more
    Google (08/08/25)
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  • IC Physical Design Flow, Principal…

    Cadence Design Systems, Inc. (San Jose, CA)
    …related experience in design and EDA (Digital Implementation/Signoff) + Understands ASIC Design implementation process and steps + Strong hands-on experience ... + Provide technical support to Cadence customers in the areas of Digital Design Implementation & Signoff including Synthesis, Place and Route, Design Closure,… more
    Cadence Design Systems, Inc. (07/18/25)
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