- Cisco (San Jose, CA)
- …are received.** **Meet The Team** As part of the team you will collaborate with ASIC design teams in the Central Hardware Group, peer Test and Product Engineers ... the test program to production. Apply sophisticated data analytics to optimize test efficiency and drive yield improvements. Collaborate with Design , SoC, DFT,… more
- Meta (Sunnyvale, CA)
- …classic algorithms to achieve product requirements. **Required Skills:** Image Processing Engineer Responsibilities: 1. Build new tools and workflows for evaluating ... and improving the visual quality and computational efficiency of vision systems 2. Perform image and video...and subjective methods 3. Collaborate with software teams to co- design image tuning firmware and algorithm for performance optimization… more
- NVIDIA (Santa Clara, CA)
- …technologies (storage, networking, compute) our chip engineers depend on. + Experience with ASIC , VLSI, CAD/EDA or mixed signal design workflow environments. + ... reshape PC gaming and modern computer graphics. As an engineer in our EDA Workflow Optimization team, you will...worldwide. You will understand workflows covering the full chip design process from inception through study, architecture, design… more
- Google (Sunnyvale, CA)
- Product Engineer , Machine Learning Accelerators _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... Circuit Board Assembly) and related system assembly. + Experience in design for manufacturability and serviceability. **Preferred qualifications:** + 5 years of… more
- Google (Sunnyvale, CA)
- Senior Product Engineer , Machine Learning Accelerators _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... Circuit Board Assembly) and related system assembly. + Experience in design for manufacturability and serviceability. **Preferred qualifications:** + Master's degree… more
- Broadcom (San Jose, CA)
- …Test plans, Verification Environment, pseudo-random tests, etc. Lead reviews with design /architecture. . Driver Verification quality and Efficiency improvements ... Functional coverage and pseudo-random testing . Must have gone through a full ASIC cycle right from Architecture development to Tapeout with full focus on… more
- TE Connectivity (CA)
- …the needs of a faster, more connected world. As the R&D Product Development Engineer - Optical System Architect (SA), you will drive the next generation of ... innovation. **Co-Packaged and Near-Package Optics Architecture Leadership** + Drive the design and system architecture of co-packaged optics (CPO) or near-packaged… more