- Amazon (Austin, TX)
- …large subsystems Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze ... debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure...analysis . Assist verification team in unit verification including test plan development . Assist with debug and bring-up… more
- NVIDIA (Santa Clara, CA)
- …leading GPUs + You will be responsible for verification of the ASIC design , architecture, golden models and micro-architecture using advanced verification ... NVIDIA is seeking elite ASIC Verification Engineers to verify the design...tools, debug tools like Verdi, GDB) + Experience crafting test bench environments for unit and system level verification… more
- NVIDIA (Santa Clara, CA)
- …leading GPUs + You will be responsible for verification of the ASIC design , architecture, golden models and micro-architecture using advanced verification ... NVIDIA is seeking elite ASIC Verification Engineers to verify the design...great teammate are huge plus + Experience in crafting test bench environments for unit and system level verification… more
- Amazon (Austin, TX)
- …responsibilities Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze ... debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure...analysis . Assist verification team in unit verification including test plan development . Assist with debug and bring-up… more
- Amazon (Austin, TX)
- …responsibilities Gate Level Simulation: Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze ... debug logic errors, and propose solutions. Work closely with design and verification engineers to validate fixes and ensure...analysis . Assist verification team in unit verification including test plan development . Assist with debug and bring-up… more
- Amazon (San Diego, CA)
- …of FPGAs using test benches, which can be reused for the ASIC implementation . Run formal verification of complex blocks to ensure functional correctness . ... the RTL against reference Matlab/C models . Develop detailed test plans and write tests, run regressions, collect coverage...Work with the design and communication systems team and participate in system… more
- Medtronic (Tempe, AZ)
- …Lives Medtronic's Test Development Team in Tempe, Arizona, is looking for a Test Development Engineer II to develop firmware and Automated Test Equipment ... culture of professional growth and cross-functional collaboration as we work together to engineer the extraordinary. This role will require less than 10% of travel… more
- NVIDIA (Santa Clara, CA)
- …tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Synthesis Engineer to join our dynamic and growing team! If you ... intelligence. What You'll Be doing: + As a Front-End ASIC Synthesis Engineer , you will own RTL...and gate level optimization tasks + Collaboration with physical design to address timing, area, congestion tradeoffs + Drive… more
- RTX Corporation (El Segundo, CA)
- …on the Product Enabling Technologies team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, ... tools and practices for continuous improvement in the group's ASIC / FPGA design flow + Contribute.../ FPGA lab validation with advanced lab equipment + Design for Test (DFT) and manufacturability issues… more
- RTX Corporation (Cedar Rapids, IA)
- …on the Product Enabling Technologies team. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, ... tools and practices for continuous improvement in the group's ASIC / FPGA design flow + Contribute.../ FPGA lab validation with advanced lab equipment + Design for Test (DFT) and manufacturability issues… more
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