- Broadcom (San Jose, CA)
- …and high speed clock constraints and specification.** + **Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and ... you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will be contributing… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- NVIDIA (Santa Clara, CA)
- …We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal ... with simulation and synthesis tools . Strong knowledge of ASIC flow, RTL/Verilog . Individual leadership and initiative to...Nice to have : . Experience on memory subsystem verification and/or performance analysis . Knowledge of System Verilog… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer** Broadcom's ASIC Product Division is seeking candidates for a DFT position at our ... way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would… more
- Google (Sunnyvale, CA)
- …documentation, effective team collaboration, proactive problem-solving, and staying current with ASIC design trends for continuous improvement. + Ensure ... in program management. + 8 years of experience in ASIC /chip design with leadership and technical ownership....associated peripherals. + Experience in UVM/OVM or other advanced verification methodologies. + Knowledge of low-power design … more
- Palo Alto Networks (Santa Clara, CA)
- …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and ... for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to… more
- Actalent (Herndon, VA)
- Job Title: FPGA Design EngineerJob Description The FPGA/ ASIC Design Engineer will play a crucial role in the architecture, implementation, and ... verification /validation through software integration tests for the delivery of...algorithms targeting ASICs/FPGAs. + Proficiency in VHDL and FPGA design /debug using Xilinx FPGA/Vivado. + Excellent analytical and debugging… more
- Medtronic (Mounds View, MN)
- …world. **A Day in the Life** We have a great opportunity for an experienced ASIC / FPGA Digital Design Engineer with RTL experience in Verilog or VHDL ... - System Verilog preferred. Our Digital Designers also support verification and lab characterization. Put your skills using UVM, C, and Python to the test! Roles and… more
- SanDisk (Milpitas, CA)
- …requirements to various functions of Memory teams to meet systems specs. + Define ASIC requirements for upcoming new NAND Flash based chips and design systems ... products + Work with Architecture and Firmware team on detailed implementation and verification plan. + Monitor NAND readiness and work with Product test teams on… more