- NVIDIA (Santa Clara, CA)
- …GPU-accelerated optimization methods. + Apply deep learning and GPU computing to improve ASIC and VLSI design tool flows. + Collaborate cross-functionally with ... Domain & Technical Expertise: Deep knowledge in EDA/VLSI (eg, synthesis, physical design , verification , timing, reliability, or CAD algorithms) combined with 5+… more
- Silvus Technologies (Irvine, CA)
- …to a fulfilling career._ THE OPPORTUNITY Silvus is seeking a **_Senior FPGA/RTL Design Engineer_** who will report to the _Director of FPGA Engineering_ on the ... the research and development process from concept to field deployment. FPGA Design Engineers are responsible for the efficient implementation of novel signal… more
- IBM (Poughkeepsie, NY)
- …SoC designs using Synopsys toolsets. You will collaborate closely with RTL designers, verification engineers, and physical design teams to ensure high test ... **Introduction** Test Design is a forward-thinking semiconductor team dedicated to...years of hands-on experience in DFT implementation for complex ASIC /SoC designs in advanced process nodes (eg, 7nm, 5nm,… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We would love to hear from you! Are you looking for a Mask layout Design Engineer role? We are looking for a Senior Mask Layout Design Engineer! ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
- NVIDIA (Santa Clara, CA)
- …is our life's work, to amplify human creativity and intelligence. Are you a Mask Layout Design Engineer? If yes, We would love to hear from you! We are looking for a ... Senior Mask Layout Design Engineer, someone who is excited to join a...technologies using Cadence tools. + You'll work multi-functional with ASIC and mixed-signal engineers to customize designs for integration… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Experience on memory subsystem verification and/or performance analysis* Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob DescriptionThe Cadence IP team develops industry… more
- Broadcom (San Jose, CA)
- …and high speed clock constraints and specification. + Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and ... you apply.** **Job Description:** Broadcom is looking for a senior level ASIC physical design engineer. In this highly visible role, you will be contributing to… more
- Lockheed Martin (Littleton, CO)
- …capture * Printed wiring board layout oversight * Parts selection * Flow FPGA or ASIC design requirements to ASIC /FPGA team to determine which functions to ... put in an ASIC /FPGA * Parts stress analysis * Board/Circuit Card Assembly...\(CCA\) worst case analysis * Board test development * Design & requirements verification for electronics components… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal ... with simulation and synthesis tools . Strong knowledge of ASIC flow, RTL/Verilog . Individual leadership and initiative to...Nice to have : . Experience on memory subsystem verification and/or performance analysis . Knowledge of System Verilog… more
- Broadcom (San Jose, CA)
- …blocks and working on initial floor plan. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static ... excellent academic standing. 2). Must have in-depth knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough… more