• Senior Principal ASIC DFT Engineer

    Northrop Grumman (Morrisville, NC)
    …making history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse ... DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC ...for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts +… more
    Northrop Grumman (07/08/25)
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  • ASIC Engineer, DFT

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies for data… more
    Meta (08/01/25)
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  • Lead ASIC DFT Engineer

    Google (Mountain View, CA)
    …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
    Google (08/27/25)
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  • ASIC DFT Engineer I, Annapurna Labs

    Amazon (Austin, TX)
    …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
    Amazon (07/02/25)
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  • ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    …of DRAM controllers is a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT , timing analysis, floor planning, ECO, ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of hard-working… more
    NVIDIA (08/28/25)
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  • System Level Product Development Engineer

    NVIDIA (Santa Clara, CA)
    …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... teams to coordinate efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working… more
    NVIDIA (06/17/25)
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  • DFT Senior Manager

    Broadcom (San Jose, CA)
    …apply.** **Job Description:** Broadcom's ASIC Product Division is seeking candidates for a DFT Manager position at our San Jose Design Center. As a DFT ... Manager, you will lead a group of highly performing DFT Engineers working on delivering high quality custom silicon...customers. The successful candidate will be responsible for leading DFT programs all the way from pre-sales through to… more
    Broadcom (08/20/25)
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  • Sr Principal DFT Application Engineer

    Cadence Design Systems, Inc. (Cary, NC)
    …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... testbenches. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
    Cadence Design Systems, Inc. (06/06/25)
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  • ASIC Engineering Technical Leader - SDC

    Cisco (San Jose, CA)
    ASIC Engineering Technical Leader - SDC Apply (https://jobs.cisco.com/jobs/Login?projectId=1434557) + Location:San Jose, California, US + Area of InterestEngineer - ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
    Cisco (08/14/25)
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  • Sr Advanced ASIC Physical Design Engineer

    Honeywell (Phoenix, AZ)
    …products for aerospace, military and high temperature applications. Relevant circuits include ASIC library cells such as logic, registers, and I/O cells; memories; ... **KEY RESPONSIBILITIES** + Lead efforts to translate customer designs into Honeywell's ASIC technology (RTL to GDSII) + Execute and address Floor-planning, Power… more
    Honeywell (08/22/25)
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