- Northrop Grumman (Morrisville, NC)
- …making history. Northrop Grumman Mission Systems, Digital Technologies Group, is seeking an ASIC DFT Engineer to join our team of highly qualified, diverse ... DoD Secret clearance.** **Roles and Responsibilities:** + Responsible for DFT (Design for Testabilty) aspects of ASIC ...for DFT (Design for Testabilty) aspects of ASIC Design thorough understanding of digital design concepts +… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC DFT Engineers within our Infrastructure organization to work on Design for Test ( DFT ) methodologies, implementation, and ... EDA tools and IEEE standards (1149, 1500, 1687). **Required Skills:** ASIC Engineer, DFT Responsibilities: 1. Develop and implement DFT strategies for data… more
- Google (Mountain View, CA)
- …related field, or equivalent practical experience. + 8 years of experience in DFT or physical design. + Experience with scan insertion, Automatic Test Pattern ... (JTAG), Internal JTAG (IJTAG) tools and flow. + Experience with DFT Electronic Design Automation (EDA) Tools like Tessent/Genus/FC/Simvision, etc. **Preferred… more
- Amazon (Austin, TX)
- …Key job responsibilities * Develop, implement and verify state-of-the-art Design for Test ( DFT ) architectures * Work with block designers to integrate DFT ... Work with physical design team to setup and implement DFT insertion flow * Develop high coverage and cost...insertion flow * Develop high coverage and cost effective DFT methodologies * Perform RTL coding and Verification *… more
- Google (Sunnyvale, CA)
- …+ Knowledge of high performance and low-power design techniques. + Knowledge of ASIC Verification, Design For Testing ( DFT ), Synthesis, Static Timing Analysis ... of experience in people management, developing employees. + Experience in ASIC development with System Verilog. + Experience in Computer Architecture, including… more
- NVIDIA (Santa Clara, CA)
- …yield enhancement and spec validation + Partner with other engineering groups including ASIC , DFT , ATE, silicon validation, fab process, software and quality ... teams to coordinate efforts and resolve silicon issues + Initiate and drive process improvements/preventative actions through root cause analysis + The ideal candidate will always look to improve workflows, products, functions and methodologies while working… more
- Cadence Design Systems, Inc. (Cary, NC)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... testbenches. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Broadcom (San Jose, CA)
- …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
- Cisco (San Jose, CA)
- ASIC Engineering Technical Leader - SDC Apply (https://jobs.cisco.com/jobs/Login?projectId=1434557) + Location:San Jose, California, US + Area of InterestEngineer - ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
- SpaceX (Bastrop, TX)
- Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering) Bastrop, TX Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... with the ultimate goal of enabling human life on Mars. SR. SOC/ ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more