- Cadence Design Systems, Inc. (Austin, TX)
- …who want to make an impact on the world of technology. We are looking for SoC/ ASIC Digital Design Engineer with experience in Design for Test ( DFT ). An intimate ... preferred. + Prior 5-15 years of professional experience in SoC/ ASIC Digital Design with focus on Design for Test... Digital Design with focus on Design for Test ( DFT ) + Should possess intimate knowledge of DFT… more
- Northrop Grumman (Jessup, MD)
- …RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion) + Proficiency with current ASIC design tools for all ... RTL to gates (RTL coding, simulation, synthesis, static timing analysis, logic equivalence, DFT insertion) + Proficiency with current ASIC design tools for all… more
- Broadcom (San Jose, CA)
- …switching ASIC DFx (Design for Test/debug & manufacturability) from DFT architecture, to implementation, verification, timing closure, ATE pattern bringup. . You ... you apply.** **Job Description:** Broadcom's CSG division is seeking candidate for a DFT lead position. The successful candidate will be responsible for leading most… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer - DFX NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the… more
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a sufficient ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- Northrop Grumman (Jessup, MD)
- …our mission! Northrop Grumman Mission Systems (NGMS) is seeking a Sr. Staff ASIC Physical Design Engineer to support our growing engineering team in advanced ... block and chip levels. + Perform physical design of ASIC designs, including floor planning, placement and routing, clock...such as Tcl, Python or Perl + Knowledge of DFT , including scan insertion and ATP + Effective communication… more
- Cisco (San Jose, CA)
- …**Meet the Team** You will be part of the Silicon One development organization as an ASIC implementation engineer in San Jose, CA. As a member of this team you will ... Impact** You will be the lead to drive the DFT /DFx and quality process through the early product life...Computer Engineering required with at least 10+ years of ASIC Hardware Development experience. + Prior experience on hardware… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team offers a unique experience for ASIC engineers, combining the resources and stability of a large, multi-geography ... startup-style team. You'll collaborate with exceptional talent with deep ASIC design and development expertise. As part of a...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- RTX Corporation (Salt Lake City, UT)
- …**Security Clearance:** DoD Clearance: Secret **Principal Electrical Engineer** **- ASIC /FPGA (Onsite)** This position is for a motivated Principal Electrical ... and information assurance products. **What You Will Do:** + Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure,… more
- Cisco (San Jose, CA)
- …Impact:** You will be in the Silicon One development organization as an ASIC Implementation Technical Lead with a primary focus on Design-for-Test. You will work ... physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. As a...networking chips. You will help lead to drive the DFT and quality process through the entire Implementation flow… more