• Senior ASIC Design Engineer , Kuiper…

    Amazon (Austin, TX)
    …Develop and maintain comprehensive gate-level simulation test plans for verifying ASIC functionality and timing. Analyze simulation results, identify and debug logic ... integrate 3rd party IP blocks . Understand low power design & the impact of DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification… more
    Amazon (06/27/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon engineering ... experience) with 2 years experience in Synthesis and Timing. + Understanding of DFT logic and hands-on experience in design closure. + Expertise in analyzing and… more
    NVIDIA (05/14/25)
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  • Senior ASIC Test Engineer

    Micron Technology, Inc. (Boise, ID)
    …advance faster than ever. We are seeking a passionate and innovative ATE Test Engineer to develop cutting-edge test solutions for our SSD and UFS controllers using ... or Perl) + Proven expertise in test strategy development, test plan definition, DFT pattern implementation (ATPG SCAN, TDF, MemBIST and repair, BSACAN, JTAG, and… more
    Micron Technology, Inc. (06/12/25)
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  • Sr. ASIC Design Engineer

    Amazon (Sunnyvale, CA)
    …by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT , UPF), Power Analysis and STA -Take the lead and work with verification ... teams to define functional coverage -Work with pre-silicon verification teams to assist in defining testplans/testbenches -Work with post-silicon validation teams to define and execute on testplans -Write high quality documents to guide and lead a scalable… more
    Amazon (07/19/25)
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  • Senior ASIC Design Engineer

    Amazon (San Diego, CA)
    …benches constructed using UVM, System C and DPI-C . Ensure that the block meets DFT , timing and power targets by working closely with the implementation team . Learn ... about requirements and solutions for systems operating in space . Drive trade-off analysis to benefit customer experience and optimization of resources (costs, power, spectrum) Export Control Requirement: Due to applicable export control laws and regulations,… more
    Amazon (07/09/25)
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  • ASIC Physical Design Engineer

    Amazon (Austin, TX)
    …to improve physical design flows and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications Bachelors' ... degree or higher in Electrical Engineering, Computer Engineering Graduation date between May 2023 and December 2025 Scripting internship/project experience with Python, Perl or equivalent Strong understanding of VLSI circuit design fundamentals Have taken at… more
    Amazon (06/17/25)
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  • Senior DFx/RTL Engineer

    Cisco (San Jose, CA)
    Senior DFx/RTL Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1447271) + Location:San Jose, California, US + Area of InterestEngineer - Hardware + ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with...physical design teams to understand chip architecture and drive DFT requirements early in the design cycle. **Key Responsibilities:**… more
    Cisco (07/22/25)
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  • CAD Flow Development Engineer

    NVIDIA (Santa Clara, CA)
    …Are you a computer engineer with a passion for automation of VLSI ASIC design? Be part of a diverse team creating NVIDIA's chip design methodology! These chips ... physical design, formal equivalence checking. + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT... ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Familiarity with Machine Learning/Deep Learning… more
    NVIDIA (07/25/25)
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  • Physical Design Engineer - Multiple Levels

    Qualcomm (San Diego, CA)
    …to help create a smarter, connected future for all. QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions ... SOC and core design team. As a physical design engineer you will innovate, develop, and implement chips and...this role involves good understanding of functional and test ( DFT ) mode constraints for place and route, floorplanning, power… more
    Qualcomm (07/12/25)
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  • Product Test Engineer

    Cisco (San Jose, CA)
    Product Test Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444752) + Location:San Jose, California, US + Area of InterestSupply Chain + Compensation ... As part of the team you will collaborate with ASIC design teams in the Central Hardware Group, peer...Operations, and with Cisco Systems NPI teams. Collaborate with DFT , Reliability, Quality, Failure Analysis and Manufacturing teams to… more
    Cisco (07/29/25)
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