• Senior Principal ASIC Static Timing…

    Northrop Grumman (Linthicum Heights, MD)
    …in HDL (VHDL/Verilog/SystemVerilog) + Experience in the full product life cycle of ASIC Design + Effective communication and presentation skills and high ... Systems, Digital Technologies Group, is seeking a Static Timing Engineer to join our team of highly qualified, diverse...propose changes to fix them + Work closely with design , verification, design -for-test and physical design more
    Northrop Grumman (10/10/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Verification Engineer ! NVIDIA is seeking an outstanding engineer to verify the design and implementation of the ... performance of PCIe and CXL designs + Understand the design , define the verification scope, develop the verification infrastructure,...the verification infrastructure, and verify the correctness of the design What we need to see: + BS or… more
    NVIDIA (07/20/25)
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  • Senior ASIC Verification Engineer

    NVIDIA (Austin, TX)
    …and intelligence. The NVIDIA System-On-Chip (SOC) group is looking for an experienced ASIC Verification Engineer ! In this position you will have the chance ... on verifying and improving the related verification methodologies for the corresponding design (RTL). For this position, you should have real passion for… more
    NVIDIA (09/18/25)
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  • ASIC Engineer , Implementation

    Meta (Sunnyvale, CA)
    …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... hierarchical reset domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and corresponding reset sequence… more
    Meta (09/20/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    … tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are ... Engineering or equivalent experience. + 8+ years experience in Physical design /Timing. + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing… more
    NVIDIA (09/09/25)
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  • Senior ASIC Engineer - DFX

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Engineer in the area of DFX ATPG flows and methodologies. Do you like to think creatively and enjoy solving challenges that ... from you! What you'll be doing: + Support the deployment of advanced Design -For-Test (DFT) and Automatic Test Pattern Generation (ATPG) solutions + Work with… more
    NVIDIA (07/26/25)
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  • Senior Software Engineer , ASIC

    NVIDIA (Santa Clara, CA)
    …years of EDA tool development in the verification field + Hands on experience with ASIC design and verification + Good with C++ and other programming languages ... stand out from the crowd: + Good understanding of Design for Testing including Scan/ATPG/JTAG. + Strong English communication....working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our GPU… more
    NVIDIA (07/29/25)
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  • Intern - ASIC Digital Design

    Micron Technology, Inc. (Minneapolis, MN)
    …that power Micron's innovative memory and storage technologies. **Position Overview** As a Digital Design Engineer Intern, you will contribute to the design ... communicate and advance faster than ever. **Department Introduction** Micron's ASIC Logic Design team is at the...than ever. **Department Introduction** Micron's ASIC Logic Design team is at the forefront of developing high-speed,… more
    Micron Technology, Inc. (09/17/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Westford, MA)
    …amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding Networking Silicon ... you will be doing: + You will drive physical design and timing of high-frequency and low-power DPUs and...level, and/or full chip level. + Analyze and optimize design constraints and synthesis parameters to achieve performance, power,… more
    NVIDIA (08/13/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the crowd:...critical paths. + Background and expertise in high frequency design closure at subsystem level. + Ability to develop… more
    NVIDIA (09/23/25)
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