• Staff Digital Systems Engineer (Ox384)

    Northrop Grumman (Linthicum Heights, MD)
    …and supporting validation at the system level. + Experience with ASIC Specification generation and verification . + Multi-Disciplinary Engineering exposure ... within the Northrop Grumman Microelectronics Center (NGMC). Boasting state-of-the-art design capabilities, multiple processing nodes, electrical testing, environmental and… more
    Northrop Grumman (07/30/25)
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  • Physical Design Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level ASIC physical design engineer . In this highly visible role, you ... and high speed clock constraints and specification.** + **Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and… more
    Broadcom (09/26/25)
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  • Senior Mask Design Engineer…

    NVIDIA (Santa Clara, CA)
    …We would love to hear from you! We are looking for a Senior Mask Layout Design Engineer , someone who is excited to join a growing and dynamic group of ... using Cadence tools. + You'll work cross functionally with ASIC and mixed-signal engineers to customize designs for integration...part in floor planning, custom layout and verifying against design rules and schematics. What we need to see:… more
    NVIDIA (10/16/25)
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  • Lead Applications Engineer - DDR…

    Cadence Design Systems, Inc. (San Jose, CA)
    …Join the High-Performance Culture at Cadence. As a Lead Technical Presales Engineer , you will use your knowledge of different memory interface standards to ... teams, definers and designers . Write application notes, user guides, articles, design ideas, new product proposals, and evaluation kit manuscripts for internal… more
    Cadence Design Systems, Inc. (10/04/25)
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  • Fpga Design Engineer

    Actalent (Herndon, VA)
    Job Title: FPGA Design EngineerJob Description The FPGA/ ASIC Design Engineer will play a crucial role in the architecture, implementation, and ... verification /validation through software integration tests for the delivery of...algorithms targeting ASICs/FPGAs. + Proficiency in VHDL and FPGA design /debug using Xilinx FPGA/Vivado. + Excellent analytical and debugging… more
    Actalent (10/19/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Candidate Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for ... way from chip level DFT specification, through to implementation and verification culminating in successfully releasing products to production. The candidate would… more
    Broadcom (09/05/25)
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  • Sr. Staff SEIT Lead Systems Engineer (a)

    Northrop Grumman (Annapolis Junction, MD)
    …and supporting validation at the system level. + Experience with ASIC Specification generation and verification . + Multi-Disciplinary Engineering exposure ... One of our most challenging new fields is Microelectronics Design and Applications (MDA), which combines the unique properties...MDA is seeking a **Sr. Staff SEIT Lead Systems Engineer ** based out of Linthicum, MD or Annapolis Junction.… more
    Northrop Grumman (08/21/25)
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  • Senior Silicon Engineer

    Microsoft Corporation (Santa Clara, CA)
    …looking for passionate, high-energy engineers to help achieve that mission. As a Senior Silicon Engineer - ASIC verification in the Data Processing Unit team ... your career. We are looking for a **Senior Silicon Engineer ** to Join our team! **Responsibilities** + Lead key...testing strategies + Work with cross functional teams, architecture, design , verification , partner teams for project execution… more
    Microsoft Corporation (10/07/25)
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  • FPGA Engineer , Platforms, Hardware

    Google (Sunnyvale, CA)
    …related field, or equivalent practical experience. + 4 years of experience working in an ASIC or FPGA design technical environment, or 3 years of experience with ... FPGA Engineer , Platforms, Hardware _corporate_fare_ Google _place_ Sunnyvale, CA,...such as AXI4, Avalon etc. + Experience with FPGA design and verification tools (Vivado, Quartus) and… more
    Google (09/28/25)
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  • Senior System SW Engineer , System…

    Palo Alto Networks (Santa Clara, CA)
    …Processor Tool Chain Development - Assembler, Debugger, Simulator + Infrastructure to support ASIC team development and verification + ASIC microcode and ... for next generation firewall products, identify performance bottlenecks and solutions, design and model protocol and sub-component offload solutions. In addition to… more
    Palo Alto Networks (10/18/25)
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